Samsung is investing in Pennsylvania State University for its work on fabricating III-V indium gallium arsenide FinFETs likely to be used at the 7nm node.

The silicon FinFET (3D fin gates on field effect transistors) have become the standard for low leakage and high performance at advanced nodes, but III-V compounds such as indium gallium arsenide (InGaAs) are faster than silicon, prompting researchers at Penn State to combine the best of both worlds. Penn State's InGaAs FinFET transistors use a novel five-gate structure grown on an indium phosphide (InP) substrate in its Materials Research Institute's Nanofabrication Laboratory.

"These FinFETs as of now have been fabricated on InP substrates," Arun Thathachary, an EE doctoral candidate working under Professor Suman Datta, told EE Times. "Samsung will own the IP generated from this project." Fellow doctoral candidate Nidhi Agrawal has also contributed to the project.

The devices enable continual CMOS scaling down to 7nm and below, and also enable new heterogeneous system opportunities in hybrid CMOS-RF and CMOS-optoelectronics.

For years, other semiconductor firms have funded research to fabricate III-V transistors on silicon substrates, including Intel, Sematech, and, more recently, Imec.

The reason everybody is trying to integrate III-V transistor channels with silicon substrates is cost. Not only are InP wafers more expensive, but the entire semiconductor industry is based on equipment optimised for silicon manufacturing. So even though Penn State is using InP wafers to prove the concept that III-V FinFETs will retain their high mobility at advanced nodes (5nm) and at lower voltages (0.5V), Samsung would eventually have to solve the problems of integrating III-V materials with complementary (n- and p-channel) metal-oxide semiconductors (CMOS) on 300mm silicon substrates.

By: DocMemory
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