Digital Core Design, an IP core provider and SoC design company, has announced the DRPIC1655X that the company describes as a low-cost, high performance, 8bit, fully static soft IP core geared to operate with fast, dual ported memory. The microcontroller targets applications ranging from high-speed automotive and appliance motor control, to low-power remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode makes this IP core ideal for applications where the power consumption aspect is critical, noted the company.

The DRPIC1655X soft core is software-compatible with the industry standard PIC 16XXX microcontrollers. It implements enhanced Harvard architecture (separate instruction and data memories), with independent address and data buses. The 14bit program memory and 8bit dual port data memory allow instruction fetch and data operations to occur simultaneously. The advantage of this architecture is that instruction fetch and memory transfers can be overlapped by multi stage pipeline, so that the next instruction can be fetched from program memory, while the current instruction is executed with data, from the data memory.

The DRPIC1655X architecture claims to be four times faster compared to standard architecture. Most instructions are executed within one system clock period, except the instructions, which operate directly on PC (GOTO, CALL, RETURN) program counter. The device is delivered with fully automated test bench, complete set of tests and DoCD on-chip hardware debugger, which allow easy package validation, at each stage of SoC design flow.

Unlike other on-chip debuggers, DoCD provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, including user defined peripherals, data and program memories, the company added.

By: DocMemory
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