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Is IP cooperation the way ahead?


Monday, October 6, 2014

Everyone knows that FPGA complexities are rising remorselessly, despite constant worries that Moore's Law is about to hit the buffers. Vendors are already shipping 20nm devices and promising that new products using various flavours of FinFET are just around the corner. These will push FPGA densities to even higher levels.

Additional capabilities allow engineers to build ever more sophisticated systems into programmable devices and to produce innovative products. Intellectual property (IP) cores provide access to advanced specialist functions without requiring the user to be an expert in the technology. Such cores feature the wisdom and knowhow of the core provider and should provide an efficient implementation in the chosen FPGA architecture. Many IP vendors focus on one area of core competency, so that their products are highly efficient and fully compliant. As a result, system architects can specify a number of complex building blocks that combine third-party IP cores with home-grown IP to create the total system.

However, this means that the poor, overstretched FPGA design engineer has the added burden of blending IP cores from several different vendors. Each core may be using a different HDL and test benches, and the interfaces (almost by definition of Murphy's Law) will be incompatible with other cores that must communicate with it. Some IP cores may even require specific FPGA resources, which can restrict placement and hinder timing closure.

Hence my question forming the title of this column: "Is IP cooperation the way ahead?" A recent announcement from two leading IP vendors—Algotronix, which specialises in all forms of AES encryption, and Adaptive Micro-Ware, an expert in secure video transport solutions—illustrates the point.

The companies have worked together in the past on an ad-hoc basis, but they say their customers will benefit from the closer association described in their announcement through smaller, more secure solutions that are highly efficient in the FPGA.

Video and encryption are two very different propositions. A video transport will typically multiplex multiple audio, video, and meta-data streams into a single bit stream. Each stream will have tight timing budgets, because excessive latency and dropped frames are unacceptable. Added to this, if the data is transported over an unmanaged network, such as the Internet, forward error correction will be required.

Encryption is all about security. Any FPGA implementation needs to be from a "known good" source to avoid the possibility of a back door. The core should be fully compliant with the AES specification and be NIST certified, or it might have severe security implications. The partially encrypted data inside the FPGA must be invisible to any observer, and the integrity of the key must be absolute. The core should be very efficient and configurable to cover different data rates and key lengths, with options for full or half duplex operation.

Combining these two technologies can provide a fast, efficient, and secure solution to transporting video over insecure networks. Copyright holders, such as Hollywood studios, are very anxious to ensure they retain ownership of their material, so they need to be confident that the digital rights management is preserved in applications such as streaming video between studios or distribution to digital cinemas, as well as video-on-demand in hotels or on aircraft.

Military and security applications range from streaming high-definition video for UAVs to border and perimeter surveillance.

Now customers can take advantage of the symbiotic tieup between Algotronix and Adaptive Micro-Ware for their secure video transport IP cores.

Many core providers have been acquired and absorbed into larger companies. As a result, they may lose the speed and flexibility associated with being small and nimble. Is IP cooperation the way for IP vendors to retain their independence?

 

By: DocMemory
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