As adoption of DDR4 finally gains steam, memory testing equipment makers are also seeing increased demand for their tools.

Teledyne LeCroy is one of the vendors benefiting from the long-anticipated transition to DDR4. It recently announced its Kibra 480 Compliance Analyzer aimed at helping DDR memory developers, implementers, and integrators verify and validate that their DDR memory design meets JEDEC compliance parameters. The Kibra 480 supports either DDR3 or DDR4, but as the latter doubles the speed of its predecessor, compliance and validation become more difficult, said Roy Chestnut, director of technical marketing and program manager for Teledyne’s DDR protocol analyzer product line.

DDR3 had its own set of issues in its early days, Chestnut said, and while the parameters of compliance are still about 90% the same, as are many of the tests, the latencies are different. “Probing the signals is a little more difficult,” said Chestnut, “so getting information out is more difficult.”

In fact, he said, perfectly good memory can fail a compliance test if not configured correctly, so the Kibra 480 has been designed for quick setup with minimal configuration. It provides immediate feedback on violations and allows users to quickly validate that their memory system meets JEDEC timing compliance. It also allows rapid identification and elimination of any problem areas and can quickly identify timing issues associated with the JEDEC defined speed bins.

Chestnut said Intel’s release of the Haswell-E server has sparked the uptick in interest for memory testing equipment since September, a phenomenon also observed by Tektronix, which recently released its LPDDR4 PHY layer test solution for high-speed, low-power memory interfaces for mobile devices.

Christopher Loberg, senior technical marketing manager for performance instruments at Tektronix, said that now that the new Intel platform has hit, the need to validate memory has significantly increased for DDR4, after a lull that stretches back to 2011, with many vendors recently re-announcing DDR4 products.

As DDR4 starts to hit the server and PC segments, LPDDR4 is making its way into the mobile devices, which presents its own challenges, said Loberg, due to lower input/output voltage of just 1.1V, higher data rates, and compact mechanical designs that limit access to test points.

Other challenges to testing, he said, include multiple changes in Vref, read burst, and write burst, which further increase the complexity to perform the tests mandated by the JEDEC JESD209-4 specification. Like Teledyne LeCroy, Tektronix aims to provide tools for design engineers that are simple to set up with quick testing cycles so they can qualify their designs.

Loberg said there are lot of different things that have to be considered on the mobile side as the architecture of the device relies on memory performance to provide the experience users expect, including quick loading of applications. There are different ways of buffering memory, he added. “There are a variety of ways to skin that cat.” What’s especially critical for LPDDR testing is that precision when connecting is essential; that’s why it’s possible to accidentally fail a device, said Loberg.

One method of addressing this is called de-embedding, where LPDDR4 interposers are employed. A physical board is used between the DRAM and the bus, which allows designers to pick up signal traffic and place it on cable or probe back to a scope. Tektronix recently introduced a LPDDR4 memory component interposer, dubbed EdgeProbe, in collaboration with Nexus Technologies.

By: DocMemory
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