According to the latest report from Yole Developpement, many assume that both the compute variety (DDR3/DDR4) and the mobile variety (LPDDR3/LPDDR4) of DDR to reach the end of their road soon as the interface allegedly cannot run at data rates higher than 3.2Gb/s in a traditional computer main memory environment. Consequently, several DRAM memory architectures based on 3D layer stacking and TSV have evolved to accommodate increasing memory requirements.

The challenges for DRAM are to reduce power consumption, satisfy required bandwidth and satisfy density (miniaturisation) all the while maintaining low cost. Applications are evolving with different demands on these basic requirements. For example graphics in a smartphone may require bandwidth of 15GB/s while a networking router may require 300GB/s.

Memory is also known to be the biggest user of power in server farms, thus there is a requirement in both portable devices and networking and server applications for low power memory solutions.

With the recent Samsung announcement of mass production of 64GB DDR4 DIMMs that use TSV technology for enterprise servers and cloud-based applications, all three of the major DRAM memory manufactures, Samsung, Hynix and Micron, have announced the commercialisation of TSV-based memory architectures.

Hynix has announced the release of multiple memory solutions over the next two years.

Emerging DRAM technologies such as wide IO, HMC and HBM are being optimised for different applications and present different approaches to address bandwidth, power and area challenges. The common element to HMC, HBM and Wide I/O are 3D technologies, i.e.

Wide I/O increases the bandwidth between memory and its driver IC logic by increasing the IO data bus between the two circuits. Wide I/O typically uses TSVs, interposers and 3D stacking technologies.

The 2014 Wide I/O 2 standard JESD229-2 from JEDEC, is designed for high-end mobile applications that require high bandwidth at the lowest possible power. Wide I/O 2 provides up to 68GB/s bandwidth, at lower power consumption (better bandwidth/W) with 1.1V supply voltage. From a packaging standpoint, the Wide I/O 2 is optimised to stack on top of a SoC to minimise power consumption and footprint. This standard trades a significantly larger I/O pin count for a lower operating frequency. Stacking reduces interconnect length and capacitance. The overall effect is to reduce I/O power while enabling higher bandwidth.

In the 2.5D-stacked configuration, cooling solutions can be placed on top of the two dies. With the 3D-stacked form of Wide I/O 2, heat dissipation can be an issue since there is no standard way to cool stacked die. The Hybrid Memory Cube (HMC) is a specialised form of the wide I/O architecture.

The HMC developed by Micron and IBM is expected to be in mass production in 2014. This architecture consists of 3D stacked DRAM layers on top of a controller logic layer. For example, four DRAM die are divided into 16 "cores" and then stacked. The logic base is at the bottom has 16 different logic segments, each controlling the four DRAMs cores that sit directly on top of it . This type of memory architecture supports a very large number of I/O pins between the logic and DRAM cores, which deliver bandwidths as high as 400GB/s. According to the Hybrid Memory Cube Consortium, a single HMC can deliver more than 15x the performance of a DDR3 module and consume 70 per cent less energy per bit than DDR3.

By: DocMemory
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