Companies such as Intel, Altera and Xilinx are developing and pushing to market their respective FPGA devices by next year in a flood of marketing claims and counter-claims. With this scenario, one can only expect that the FPGA market in 2015 will be anything but boring.

Let's start by recalling what happened during 2013 when both Altera and Xilinx rolled out their 28nm families built by TSMC. Xilinx held the accolade of having the largest device (XC7V2000T) with nearly two million equivalent LUTs. This part is built using 2.5D packaging technology and was dismissed by John Daane, CEO of Altera, as a limited volume prototyping device. No doubt ASIC prototyping is not a huge market, but add military, high performance computing and applications such as scientific and financial acceleration, and the volume builds up. Why this is significant will become clear.

TSMC was offering a planar 20nm process in 2013, but the industry was sharply divided by the perceived benefits of this technology. In fact, some companies such as Nvidia stated that a 20nm process is of no benefit, as the tooling and wafer costs are both higher than 28nm with the result that there is no reduction in cost per transistor.

Having said this, Altera has created a mid-range Arria 10 family using the TSMC 20nm process. But it decided to skip using the 20nm node for its Stratix family in favour of focusing its engineering resources and moving straight to using the Intel FinFET process at 14nm for its next generation high-end product. This looked like an inspired move at the time, because Intel was widely reported as being two years ahead in terms of process technology. Intel was also producing devices at the 22nm node using the technology that it calls Tri-Gate. This strategy would give Altera a lead over arch-rival Xilinx that promised to be nearly insurmountable.

In contrast, Xilinx embraced 20nm for both the mid-range Kintex and high-end Virtex families using an architecture that it called UltraScale. The company shipped its first 20nm product to a customer in late 2013 and has continued the rollouts through 2014. The largest 20nm Virtex part is slated to have 4.4 million LUT equivalents. Now, probably few reading this column will be using the "biggest" and "baddest" FPGAs, but the top customers that both Altera and Xilinx service do use them. Applications such as communications, defence and data centres will use a range of complexities, and half of the revenue of the FPGA industry is in the high-end product ranges. So, if Xilinx has exploited the current situation fully, it should give it a big advantage, because once engineers gain familiarity with the latest tool flow they tend to stay with it for their next design (FPGA vendors call this "incumbency").

Meanwhile, Xilinx also committed to use the TSMC 16nm FinFET technology for products beyond 20nm.

It was initially planned for Altera to have samples around now, but the much publicised (and rumoured) race to get to production at 14nm has seen time frames for initial samples move into 2015. Altera expects the combination of the process and a novel HyperFlex architecture in Stratix 10 to double the performance of existing devices with significantly better power performance. They have also spoken of a monolithic device of over 4M LUTs, which would rival the Xilinx 2.5D device

At the same time, Samsung and pure-play foundries such as TSMC claim massive strides with their own versions of FinFET technology. In fact, Moshe Gavrielov, the CEO of Xilinx, told Wall Street analysts in October that he hopes to sample devices manufactured by TSMC in "early 2015."

So the gap between Altera and Xilinx is either closed or at least is significantly narrower than it appeared back in 2013. Altera has ceded the high-end to Xilinx through 2014 while gambling that devices processed by Intel would propel it into a strong leadership position.

By the way, this may very possibly still turn out to be the case. Intel has vital production experience with both 22nm and 14nm FinFET processes. Nobody doubts that the move from producing a few samples (called risk production) to full blown production is fraught with difficulties, only time will tell on that one.

The technical press has also pointed out differences between the Intel 14nm and TSMC 16nm process. The route TSMC chose to follow to get quickly to FinFET gave no scaling advantage at 16nm over the 20nm die size. Various claims showed that the TSMC die size would be significantly larger than the Intel equivalent. A larger die size translates to a higher cost (if the yields from processes are similar). This would put Xilinx at a disadvantage. TSMC, however, has disputed this point and produced two FinFET process variants. It recently announced its 16nm FinFET Plus (16FF+) enhanced process is now in risk (early) production.

However, with both FPGA companies reporting gross margins of close to 70 per cent, it would be possible for either company to take an initial hit on margin to gain key socket wins, especially as both know that yield will increase as the process matures. Another unknown (at least to me) is the wafer cost. Intel is rumoured to have high prices, while TSMC live and die by offering competitive foundry prices.

The final variable is a big one. The design tools used by the designers are the key to success. They are highly visible, and the complexities and speeds of FinFET FPGAs will be a severe test. In August, Altera shipped FinFET design tools to beta users, and it reported that customers are seeing a doubling of performance across a range of designs.

The battle for FPGA market share continues unabated. 2015 promises to see initial product releases and (no doubt) a deluge of marketing claims and counter-claims. One thing is certain, 2015 will not be boring.

By: DocMemory
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