In its invited paper [Ref 1] at IEDM 2014, IBM offers a headline-grabbing position: For PCM, non-volatility/data-retention is no longer essential. It might cause many PCM developers, who for a long time have been struggling with the problem, to breathe a sigh of relief, albeit perhaps short lived in the light of what follows.

As always the devil is in the detail, and, in this case, it was for the application of PCM (phase change memory) to SCM (storage-class memory). SCM is defined as the location in a multi-processor memory hierarchy between the NAND-flash based solid state drives (SSDs) as the system memory and the SRAM closely linked to the processors. To date, because DRAM in its SCM role is about three orders of magnitude faster than Flash, it is able to deal with the frequent fetches from the system memory and now more often occupies this space.

The problem is the growth of processor parallelism while system memory latency is remaining roughly constant. The solution to the problem of servicing the multiple fetches from system memory is to add more DRAM. This increased cost of adding more DRAM in order to maintain bandwidth is imposing an unacceptable cost burden, so this could open an opportunity for PCM.

The proposition in the paper is that for PCM in an SCM role, long-term non-volatility is not essential. However, what is essential is a long list, summarized of essential developments including: a need to optimize the critical and performance limiting SET operation; low-power operation; high performance, write/erase endurance; high bit density per chip; scaling; and low cost. SCMs have low read to write ratios, so to reduce switching power dissipation between read and write operations, diodes as matrix selector devices will need to be replaced with vertical surround gate (VSG) MOSFETs, where it is claimed it should be possible to achieve a 6F2 cell size similar to that of a DRAM.

By: DocMemory
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