The end of lithographic scaling of DRAM and NAND somewhere between 16nm and sub-10nm has been a popular call for the last few years, with many touting the emergence of new memory types including phase change RAM (PCRAM), ferro-electric RAM (FRAM), magneto-resistive RAM (MRAM), and more recently, resistance RAM as replacements (ReRAM and CBRAM).

Over the years TechInsights has analyzed PCRAM from Numonyx and Samsung, FRAM from Ramtron and MRAM from Freescale and its spin-off Everspin. These devices have found niche applications, but are not seen as replacements for NAND or DRAM due to scaling or power consumption constraints. Resistive RAM, on the other hand, features low power consumption and a small cell area; both compelling reasons for their adoption as a non-volatile memory.

Adesto and Panasonic are two companies that have brought two variations of resistance RAM to market. Adesto offers stand-alone memory chips ranging from 32 kb to 128 kb of conductive bridge RAM (CBRAM) for use in low power applications such as the internet of things (IoT). Panasonic is offering an 8-bit MCU with embedded ReRAM that may be used for portable health care applications, security equipment and sensor equipment. These are still niche applications, so pose little threat to DRAM or NAND in the near future.

The end of scaling for planer NAND and DRAM is real and the likes of Samsung, Micron, SK-Hynix and Toshiba are working on 3D architectures for these devices. Samsung for example released its 3D V-NAND memory in the fall of 2014 where it is being used in solid state drives (SSD) and AMD is expected to use SK-Hynix’s high bandwidth memory (HBM) in its upcoming 390X GPU.

It timely to look at products from both Adesto and Panasonic.

Adesto uses a conductive bridge technology for their RM24EP128KS, one-transistor one-resistor (1T1R) CBRAM product, and this is based on a silver/germanium sulfide/tungsten memory cell as shown in below. CBRAM relies on the formation of a conductive filament in a solid electrolyte (set) or its rupture (erase) due to an applied bias voltage. An oxidizable electrode such as silver or copper provides a source of metal ions that form conductive filaments in an insulating electrolyte. Adesto uses a silver anode for the ion reservoir, germanium sulfide chalcogenide glass as the electrolyte, and an inert tungsten cathode.

A positive bias (set) applied to the silver anode causes silver ions to migrate into the germanium sulfide layer, creating conductive filaments to the bottom tungsten cathode (conductive bridge). A negative bias (erase) reverses this process.

Silver and germanium sulfide are both unusual materials for a semiconductor foundry and Adesto’s business model is fabless. So there are limited options as to who can make the devices. In this case, Adesto has partnered with Altis Semiconductor, a specialty foundry based in Corbeil-Essones, France. The partnership is fairly close as Altis took an equity stake in Adesto in 2011[1], which also gave them a license to Adesto's CBRAM technology.

Altis's technology roadmap (circa 2013) shows the eCBRAM technology as being under development on a 130nm CMOS process[2], but it now appears to be in production with the Adesto CBRAM.

We should point out that Adesto published a paper in 2013[4] where they introduced a second generation CBRAM using an amorphous alloy containing a semiconducting element for its anodes, and an amorphous oxide as the switching layer. This 2nd generation cell is said to offer improved data retention after solder reflow operations as compared to the 1st generation CR+BRAM devices.

Panasonic is the second company that TechInsights examines that is offering resistive RAM product (ReRAM) with their MN101LR series of microcomputers. The microcontroller is fabricated at Panasonic’s former Tonami fab using a 180nm CMOS process. The Tonami fab is now operated as a joint venture with TowerJazz.

Panasonic uses a binary transition metal oxide (tantalum oxide) as a variable resistance layer sandwiched between an upper electrode (iridium) and a lower electrode (tantalum based electrode). Panasonic’s ‘319 patent further describes the tantalum oxide as having two sub-layers[5], where a bottom tantalum oxide layer is formed by the reactive sputtering process of a Ta target to form an oxygen deficient layer (TaO1.43).  This deposited tantalum oxide then undergoes an oxidation process to increase the oxygen content of its upper surface to form TaO2.45, which is close to the stoichiometric Ta2O5.

The resistance of the tantalum oxide can be switched from a high resistance to a low resistance state by the application of a negative bias voltage pulse to the top electrode, and switched back to a high resistance state by applying a positive voltage pulse to the top electrode.

Panasonic provides few hints as to how the ReRAM cell works though they do indicate in their ‘319 patent that the oxygen deficient layer (TaO1.43) is somewhat conductive and the nearly stoichiometric layer (TaO2.45 ) is resistive and that the resistive switching occurs in the TaO2.45 layer. In a 2012 paper[6], Panasonic makes reference to conductive filaments being formed in the TaO2.45 with oxygen vacancies playing a role.

Oxygen vacancy hopping and Frenkel-Poole conduction mechanisms were early explanations for the switching behaviour, but recent reports suggest Redox reactions between the upper TaO1.43 layer and the overlying iridium electrode are responsible for the resistance change. We may not know the physical mechanism as to how the ReRAM works, but work it does.

There are perhaps limited opportunities for Adesto and Panasonic to scale their memory cells to smaller geometries. Adesto’s use of Ag and GeS2 likely restricts their fabrication to the specialty foundry, Altis, who is fabricating the devices on a 130 nm process. And Altis’s product roadmap is not showing a smaller process node than the current 130nm. Adesto might be able to overcome this lithography limitation by running the front end processing through another foundry, using Altis to fabricate the Ag and GeS2 memory cell layers, and completing the wafer fabrication back at the first foundry. The logistics might be daunting, but doable.

Panasonic might have better options for a process shrink as their foundry partner, TowerJazz, has process offerings down to 45nm. And Panasonic has processor design and fabrication experience at the 45nm node with their MN2PS009 image processor used in the Olympus E-P3 camera, and at 32nm node with their MN2WS0150 HKMG processor. Designing a process shrink for MN101LR05D is well within their abilities.

Neither product is destined to become large scale commodity memory, but their targets markets; IoT and portable systems, do not require this. The likes of Samsung, SK-Hynix, Toshiba, and Micron would be the foundries most likely to produce ReRAM based commodity memory. By way of example, Samsung demonstrated a vertical resistance RAM (VRRAM) fabricated using a 3D process at the Electron Devices Meeting (IEDM) in 2011[7]. A vertical structure was used to make these devices, having a vertical central TiN electrode, coated with a TaOX storage layer, and surrounded by a W/TiN horizontal electrode. Horizontal electrodes are stacked one on top of the other to create the VVRAM structure. Samsung mentions the scalability of the VRAM to 32 or higher layers, which is quite plausible given the 39 metal gate layers used in their recently released 3D V-NAND Flash memory.

Micron and Sony, for their part, demonstrated a 16Gb ReRAM at the 2014 ISSCC conference[8] fabricated using a 27nm process with a 6F2 cell size. A dual-layer CuTe/insulator forms the resistive element. Sony has talked up the possibility of 16 Gb ReRAM storage-class memory product being ready in 2015.

So ReRAM is not quite ready for duty in our cell phones, but sometime soon they will show up.

By: DocMemory
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