Researchers at IBM have found a way to address two critical challenges affecting the feasibility of multilevel-cell (MLC) storage in phase-change memory (PCM).

At the International Reliability Physics Symposium last week, IBM Research presented a paper outlining how it dealt with the phenomenon of resistance drift and the impact of temperature, which has been a barrier to MLC PCM. Known by a number of different names, including PRAM and C-RAM, PCM is one of the more mature, emerging non-volatile memories (NVM), offering low read/write latency, high throughput performance and high endurance, while also being highly scalable.

PCM is not as fast as DRAM, but faster than flash. In an interview with EE Times in the heels of presenting at the symposium, paper co-author and lead researcher Milos Stanisavljevic noted that PCM offers relatively fast write performance, but not as fast as magnetoresistive random-access memory (MRAM). One of PCM’s attractive features compared with other NVMs is MLC storage, which is achieved by using the intermediate resistive states for storing information, in addition to the low and high resistance levels.

MLC is essential for decreasing the cost per bit of PCM and making it competitive, said Stanisavljevic, and providing the capacities needed by applications associated with big data. Moderate data retention in the presence of temperature variation is also necessary, and one of the challenges Stanisavljevic and his team tackled was data retention in MLC PCM, which can be significantly degraded due to resistance drift and noise fluctuations.

Drift, which is the change in resistance of the stored levels over time, explained Stanisavljevic, is one of the key barriers to realizing MLC PCM because it limits the number of levels that can be stored and reliability retrieved in the cell. This drift can be attributed to the variation in the activation energy of phase-change materials with time.

The research paper, entitled “Phase-Change Memory: Feasibility of Reliable Multilevel-cell Storage and Retention at Elevated Temperatures,” noted that the cell state is typically quantified by the resistance metric as the electrical resistance measured at a low bias voltage to avoid threshold switching — leading to potential disturbance of the programmed state during readout. Meanwhile, the low-field resistance exhibits a number of unwanted characteristics, such as temporal drift and poor signal-to-noise ratio at high amorphous volume, which are detrimental to MLC storage reliability.

The researchers addressed the problem of MLC data retention in PCM in the presence of temperature variation in a practical setting. They introduced a new non-resistance-based, drift-resilient cell-state metric, and demonstrated that reliable 2 bits-per-cell storage and subsequent data retention was possible on a 64 kcell PCM array.

The paper noted that a non-resistance-based cell-state metric has better immunity to resistance drift and also exhibits a wider signal range; it is also a weak function of the activation energy, so it offers significant tolerance to drift.

Stanisavljevic said by applying advanced, non-conventional cell readout metrics, IBM Research was able to demonstrate reliable 2 bits-per-cell storage and subsequent data retention in PCM cell arrays in the presence of temperature variation of the 50 degree Celsius magnitude. Addressing reliability and retention makes MLC storage a practical possibility in PCM chips.

A year ago at the 2014 Non-Volatile Memory Workshop, IBM demonstrated how to integrate PCM into a solid-state memory hierarchy, and it showed its first PCIe-based prototype board for storage systems. IBM’s presentation described its architecture, compared it to flash-based solid-state drives, and proposed a server system that eliminated the hard-disk drive in favor of a memory hierarchy using both flash-based arrays and PCM-based arrays. In comparisons, the PCM-based arrays outperformed flash.

By: DocMemory
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