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Memory architecture is the key to "instant-on" gratification


Tuesday, June 2, 2015

The concept of 'instant on' has been around for quite some time now, and I don't the technology will be going anywhere soon. Consumers these days are drawn to devices and products that actually deliver what the word 'fast' aims to. Fast set-up, fast battery recharge time, fast boot process...the list goes on.

Memory has emerged as a key differentiator in how embedded designers are achieving the user experience (UX) that today's consumers expect: instant on.

We live in a world where instant gratification and multitasking are the norm. We want what we want, when we want it. Consumers have come to require and expect innovative solutions that provide instant access to increasing amounts of heterogeneous information types, regardless of time, location, or device used. And if this isn't a big enough shoe to fill, consumers also want those devices to be as stylish, small, portable, and as low power as possible.

Due to this increased focus on intelligent devices, and the network of such devices, called the Internet of Things (IoT), semiconductor vendors and embedded developers are feeling the pressure to develop innovative products swiftly. In turn, embedded designers are feeling the pressure to choose a solution to address this wide range of design requirements to meet end-user preferences. It can be overwhelming to say the least.

A key expectation for the user experience (UX) is "instant-on" operation, and boot time is the central challenge that plays into this instant-on trend. Automotive dashboard development is a good example of where this trend is very present. But we're also seeing instant-on affecting many other industrial and consumer applications.

Memory is critical in instant-on operation. Using compressed root-file system images to save NV memory space, for instance, and unpacking it into RAM for execution will add additional seconds to the boot process. In fact, most systems that take more than 10 seconds to boot spend the majority of that time in MCU processing of the compressed code.

Although in some instances applications will be able to use a single memory architecture, in order for applications of 10MB or 20MB to boot in a few milliseconds high-end systems need to use a hybrid combination of flash architectures. Parallel NOR flash has emerged as a key solution for designers to provide execute-in-place (XIP) boot code in devices with modest code size that require a fast start-up, Parallel NOR flash delivers fast and secure boot, which also gives consumers a rich and interactive UX. Whether you're looking for a standard interface, page-mode, burst or simultaneous read/write, there is a parallel NOR flash solution for your application. This type of memory can be found in automotive, consumer and mobile products including GPS, smartphones and e-readers.

On the other hand, automotive electronics, home and industrial controls, and high performance consumer applications are using increasingly sophisticated graphical user interfaces (GUIs) that execute out of RAM to enhance and simplify the interaction between user and device. The higher-resolution images, animations and video that result from more sophisticated GUIs in turn creates a higher demand for read throughput from the flash memory where this information is archived. At the same time, however, many of these applications need compact designs, and parallel NOR flash typically needs 40 or more pins in their address and data interface.

In these compact, high-performance applications, embedded developers are using newer quad serial peripheral interface (SPI) NOR flash with enhancements such as double data rate (DDR) mode to satisfy the growing demand for memory density while keeping interface pin count down. With SPI NOR flash, designers have a low pin count.

By: DocMemory
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