By combining a novel architecture, room temperature processing and a high-density resistive material stack, professor James Tour at Rice University has produced a 3-D stackable nonvolatile resistive random access memory (RRAM) that outperforms competitive designs in both speed and bits-per-crossbar.

The key is a material stack that has a built in Schottky contact per bit thus taking the place of the diode required by the most efficient designs to date, and he claims it sports ultra-low leakage (sneak) currents, thus enabling up to 162-Gigabit (20-GByte) crossbar arrays.

 In an online video, slices taken from a tantalum oxide-based memory developed at Rice University show the partially interconnected and randomly distributed internal pores in the material.(Source: Rice University)

"Our group's ultrahigh-density nonvolatile resistive memory uses a 3-D material that can be fabricated at room temperature," professor Tour told EE Times. "Each device shows excellent selector-less memory on-off ratios--higher than 10 at 3.6 volts."

The Tour group at Rice has been working on RRAMs for many years, and has licensed previous versions for manufacturing. Its previous RRAM design using silicon dioxide as the active material has been licensed by a Tel Aviv-based company called Weebit Nano Ltd., according to Tour.

"Weebit in Israel has licensed our previous work on resistive memories which uses many of the same principles as our newest design," Tour told us.

The current materials stack has many refinements over the original design. What's common is that the two-terminal resistive material is sandwiched between metallic crossbars, the density of which determines the density of the memory array. The density of the array, in turn, is limited by the ratio between the "on" resistance compared to the "off" resistance--10-to-1--for the current material, compared to the leakage (sneak) current through adjacent memory cells that are not being addressed (crosstalk).

Tour's current material stack has very little "sneak" crosstalk when addressing the two-terminal bit cells in-between the x- and y-crossbar lines, enabling up to 162-Gbits (20-Gbytes) memories to co-exist in a single crossbar.

The material stack starts with a metallic contact at the bottom (platinum in the proof of concept prototype, but nearly any metal will do, according to Tour) on top of silicon-dioxide insulating layer atop a standard silicon wafer. On top of the metallic contact is a pure tantalum with a nano-porous layer of tantalum-oxide atop the pure tantalum. Ten atomic layers of graphene (multi-layer graphene, or MLG, in the diagram) cap the tantalum-oxide, followed by a top metallic electrode.

The memory cell switches on and off by starting out with all zeros--no direct connections between the crossbar electrodes. However, when a programming voltage is applied across two perpendicular crossbars, it causes the oxygen to migrate upward, allowing an all-tantalum filament to form across the porous-tantalum oxide toward the upper electrode. When it hits the graphene barrier layer current flows 10-times better than originally thus creating a "1" in the bit cell.

To reprogram as a zero, a high-voltage signal is sent through the crossbar to erase the cell by knocking out a few atoms of tantalum from the filament. If a one is later desired the low programming voltage is reapplied and the filament reconnects.

The process is very fast, according to Tour, and can be repeated indefinitely, but best of all consumes 100-times less energy than the nearest competitive design (for details see table S1 in the supplemental materials for the paper Three-Dimensional Networked Nanoporous Ta2O5–Memory System for Ultrahigh Density Storage in the American Chemical Society journal Nano Letters).

In the paper, there are many more details about how the control voltage can switch between ohmic and Schottky behavior, how the oxygen vacancies (holes in the tantalum-oxide arrays where oxygen atoms should be) migrate, how the tantalum/tantalum-oxide versus the tantalum-oxide/graphene interfaces work, and how the negatively charged oxygen ions create a diode-like barrier that nixes crosstalk.

Two hurdles to commercialization remain, according to contributor to the paper, professor Gunuk Wang at Korea University (Seoul). Researchers need a way to control the size of the nano pores and the fabrication of a dense enough crossbar to prove the concept of addressing ultra-dense individual bits.

Other contributors to the work at Rice included former research scientist Jae-Hwang Lee (now at University of Massachusetts) and post-doctoral researchers Yang Yang, Gedung Ruan, Nam Dong Kim and Yongsung Ji.

By: DocMemory
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