AMS continues to invest in and extend its analogue foundry business.

Last month the Austrian semiconductor maker announced a government partnership in the US to build a new 8-inch fab in New York.

The company has now added to its foundry offering in Europe with an enhancement of its 0.35µm high voltage CMOS process which will offer more dies per wafer.

Called its H35 process, it makes use of voltage scalable NMOS and PMOS transistors to lower on-resistance and so reduce die area per device.

According to AMS: “Using an optimized 30V NMOS transistor in power management applications instead of a fixed 50V transistor results in an area saving of approx. 50%.

“A 60V optimised NMOS device results in 22% less area when compared to a standard 120V NMOS transistor.”

Typical devices fabbed in this process include MEMS drivers, motor drivers, switches and power management ICs.

The foundry is automotive (ISO/TS 16949) and medical (ISO 13485) certified.

According to Markus Wuchse, general manager of ams’ Full Service Foundry division, the company ios one of the first foundry’s to offer scalable HV transistors.

“Our process design kit as well as our high voltage (HV) process expertise enable our partners to optimise their HV integrated circuits towards area and on-resistance, which immediately results in more dies per wafer,” said Wuchse.

The set of voltage scalable transistors including device layout generator (PCells), simulation models, verification rule decks for Calibre and Assura as well as documentation such as Design Rules and Process Parameters documents can be downloaded by registered users from the company’s secure foundry support server.

By: DocMemory
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