Researchers at the University of Toronto’s Integrated Systems Laboratory have have created a 20 Gb/s single-ended die-to-die transceiver to address some of the challenges presented by the technology likely to replace double data rate (DDR) memory.

“It’s clear the end of DDR is in sight, especially for high performance computing,” said Anthony Chan Carusone, a professor of electrical and computer engineering at U of T. The best alternatives on the horizon – memory stacked on top of a processor or stacked memory next to the processor – both present a series of challenges when balancing density, low latency and heat dissipation. If a memory cube is placed next to the processor, the heat dissipation issues are addressed, he said, but there needs to be an interface. “That’s really where the research comes in.”

Chan Carusone and PhD student Behzad Dehlaghi proposed a link architecture, a transceiver circuit design and a package solution to create this new die-to-die link. In telephone interview with EE Times, they outlined how the proposed transceiver uses CMOS logic-style circuits and a passive equalizer in the transmitter to reduce the power consumption, which is fully explained in their research paper, A 20 Gb/s 0.3 pJ/b Single-Ended Die-to-Die Transceiver in 28 nm-SOI CMOS. The interface connects a CMOS memory controller die at bottom of DRAM stack and the processor and achieves high density at a high data rate per pin,” said Chan Carusone.

Work has been done by industry players, said Dehlaghi, but not at significantly high densities, so there was little loss in channels and a low power was easily achieved. Single-ended signaling is used to maximize the density of the IOs using fewer bumps and wires than fully-differential signaling, he explained, while CMOS circuits are used in the building blocks of both transmitter and receiver to minimize the power consumption.

At the same time, he said, a transmitter passive equalizer was used to compensate for channel lost, and the receiver is able to generate a voltage reference signal from the incoming data using an internal reference generator. In the lab, the transceiver prototype was implemented in 28 nm FD-SOI CMOS technology and it operated at 20 Gb/s consuming only 0.3 pJ/bit of energy including a 4-to-1 multiplexer, transmitter, receiver and 1-to-4 demultiplexer.

As Dehlaghi and Chan Carusone outline in their paper, having the equalization in the transmitter, decreases the amount of low frequency current being drawn from the transmitter power supply. This results in significant power savings. The passive equalizer also mitigates one of the main issues of single-ended signaling which is power supply noise. Normally the power supply distribution network has a peak impedance around hundreds of MHz and drawing currents at those frequencies may result in a lot of power supply noise. By using a passive equalizer and shaping the transmitter current spectrum mostly to higher frequencies, the noise on the power supply is reduced.

For the transceiver/receiver design, an on-chip parallel PRBS7 generator is used to generate quarter-rate data in the transmitter. A half-rate differential clock signal is provided from off-chip and is divided into quadrature clock signals on-chip. The quarter rate PRBS7 signals are then serialized in a 4-to-1 multiplexer using the quadrature clock signals. The full-rate signal goes through a pre-driver and is delivered to the channel using the output driver.

The passive equalizer is programmable and can be bypassed using EQ BP switch. The receiver front-end comprises a termination impedance and a pre-amplifier stage that also extracts the reference signal from the incoming signal. Finally, the received signal is deserialized by a factor 4 and sent off-chip.

In the experiment that Dehlaghi and Chan Carusone outline in the research paper, a transceiver prototype was fabricated in 28-nm with two identical transceiver dies flip-chip mounted onto a silicon interposer. The interposer chip included the interconnects between two dies as well as more decoupling capacitors for the power signals.

Ultimately, the researchers were able to demonstrate that he proposed transceiver can be used on both organic substrates and silicon interposers and consume 6.1 mW power at 20 Gb/s over a 2.5 mm interconnect with 10.7 dB loss at Nyquist frequency and 4.8 dB loss at DC. The energy efficiency of the proposed transceiver is mainly due to the use of CMOS building blocks, minimizing current in the transmitter to receiver signal path, and lowering the signal swings on the channel.

By: DocMemory
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