Additional details have been released of the resistive RAM (ReRAM) made using a 16nm logic FinFET manufacturing process. A full paper is expected to be presented on a 1Kb memory array of such devices at this year's International Electron Devices Meeting (IEDM) in December.

Paper 10.5, 1Kb FinFET Dielectric (FIND) RRAM in Pure 16nm FinFET CMOS Logic Process, written by Hsin Wei Pan et al. of Tsing Hua University in Taiwan but also attributed to multiple authors from foundry TSMC.

The organisers of the conference have released diagrams that show a little more of the structure and that the memory does not require a separate specialised device to contain the hafnium oxide non-volatile memory. Instead each memory cell is based on three fins with the high-k layer used as the memory element.

The images in schematic and transmission electron microphotograph appear to show the unit cell composed of two FinFETs with one used as the selector switch. The second is connected to word line but what remains unclear is whether the memory switch is contained in one or both of these FinFETs.

The memory cell size is given as 265nm x 285nm, an area of 0.07632µm2 and comes with the particular benefit of not requiring any additional mask or process steps above that of the conventional logic process. The memory array is said to exhibit low-voltage operation, good retention and excellent reliability.

By: DocMemory
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