In the year that marks the 50-year anniversary of Moore’s Law comes the eager announcement from IBM of its breakthrough 7 nm test chip, beating founding father Intel to the latest holy grail of ever increasing density at an atomic level.

In the race to 7 nm, IBM demonstrates the drive for companies to explore new avenues, get creative with transistor and gate design and exploit specialized techniques in order to meet the increasing challenges of ever-decreasing chip geometries.

Although the announcement represents an industry milestone in the quest for miniaturization, such advances in density and performance come at a cost. A particular challenge is the increasingly complex power requirements demanded by the lower core voltages, higher currents and tighter tolerances of such new chips. This is magnified at the board level, where it is forcing power system engineers to seek out novel solutions to a problem that’s not going to go away anytime soon.

Massive increases in transistor count have now made it possible to implement multiple high-speed processors on a single die, each running at speeds of up to 3 GHz. Such advanced processors and logic devices may be exceptionally powerful, but they’re also very delicate with supply voltages being driven below 1 V. With today’s processors running at 100 W or more, this means currents are starting to exceed the 100 A mark at the point of load.

As well as dropping core voltages, and soaring current values, the reduced geometry has a considerable impact on voltage tolerances. For example, a deviation in voltage of just 2% could result in a processor shutting down. Consequently, maintaining ever tighter transient response specifications on the voltage rails supplying these atomic chips is becoming a big issue for engineers.

The pressure to deliver energy efficiency from these high-current, low-voltage systems means that the processors and support logic need to move into lower-power modes frequently, whilst being able to restore full capability extremely quickly without suffering from voltage deviations. Transient response coupled with accurate power delivery is therefore vital in such high reliability systems.

Incorporating a digital power controller into the traditional point-of-load (POL) voltage converter is one way power designers are addressing these accelerating power challenges. Digital power is allowing for much more advanced compensation and control functions than with existing analog circuit designs.

A key advantage of digital implementation is that it allows flexible control architectures, e.g. having multiple non-linear loops operating in parallel. Digital POL modules deliver an improved response capability with enhanced overall performance that ultimately provides a superior power delivery solution. CUI’s latest POL converters take advantage of the functionality built into digital PWM controllers such as Intersil’s ZL8800 family to provide stable power with the ability to react quickly to sudden changes in load conditions. In the latest generations of chips, load steps of 50, 60 or even 80 A are not uncommon. Power delivery architectures based upon digital POL modules make it possible to deliver power to the atomic chips within the specified tolerances.

Packing more processing power onto a board potentially delivers significant space savings at the system level - particularly in cloud computing and data communications applications - but not if this space is then lost to larger power supplies needed to cope with the increased load currents. Instead, with the drive towards 100 A and beyond, power engineers will need to be innovative and employ new thinking on multiple fronts. CUI’s most recent release to address this space, the NDM3Z-90 series, delivers 90 A at as low as 0.6Vout. To support even higher current applications, users can parallel up to 4 units together to achieve 360 A. And thanks to the advanced compensation schemes discussed above, the use of external decoupling capacitors can be greatly reduced, allowing designers to take greater advantage of the space savings offered by the lower chip geometries.

So IBM’s announcement of its 7nm test chip has shown that Moore’s Law is not done yet. The challenge now for power designers in meeting the complexities of greater functionality in a smaller space that these chips bring, is in coming up with novel ways to offset the requirements of their low core voltage, coupled with the high currents needed to drive them, and voltage tolerances that are tighter than ever before. As ever, the power industry will innovate…

By: DocMemory
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