Altera Corp. has unleashed what it flaunts as the industry's first heterogeneous System-in-Package (SiP) devices that feature stacked High-Bandwidth Memory (HBM2) from SK Hynix with high-performance Stratix 10 FPGAs and SoCs. The Stratix 10 DRAM SiP devices are intended to meet the most demanding memory bandwidth requirements in high-performance systems, stated the company.

Stratix 10 DRAM SiP claims to offer over 10X higher memory bandwidth relative to discrete DRAM solutions that are available today, noted Altera. This unprecedented level of bandwidth is required in data centre, broadcast, wireline networking and high-performance computing systems, which are processing an ever-increasing amount of data.

Altera is the first company to integrate this breakthrough 3D stacked memory technology alongside an FPGA, the company indicated. Stratix 10 DRAM SiP enables users to customise their workloads and achieve the highest memory bandwidth in a power-efficient manner. Altera is actively working with over a dozen customers to integrate these DRAM SiP products into their next-generation high-end systems.

Heterogeneous SiP products from Altera are enabled by using Intel's Embedded Multi-Die Interconnect Bridge (EMIB) technology. EMIB technology uses a small high-performance, high-density silicon bridge to connect multiple die together in a single package. EMIB technology features very short traces between die, allowing Altera to cost-effectively build heterogeneous SiP devices that provide higher performance and higher throughput at lower power compared to interposer-based solutions.

Altera's heterogeneous SiP strategy is to integrate into a single package a monolithic FPGA with advanced components, such as memory, processors, analogue, optical and various hardened protocols. Altera's highly integrated SiP products will address the most demanding performance and memory bandwidth requirements for high-end applications in the communications, high-performance computing, broadcast and military segments.

SK Hynix's HBM2 provides very high bandwidth while using less power in a substantially smaller form factor compared to competing memory solutions. HBM2 vertically stacks DRAM die and interconnects them using through-silicon vias (TSVs) and microbumps. Integrating the HBM2 in a heterogeneous SiP implementation enables Altera to package the DRAM memory as close to the FPGA die as possible, which shortens wire length and delivers the highest memory bandwidth at the lowest power.

Customers can get started on their Stratix 10 designs using the Fast Forward Compile performance evaluation tools. Altera will start shipping Stratix 10 FPGAs and SoCs in 2016 and Stratix 10 DRAM SiP products will start shipping in 2017.

By: DocMemory
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