The smallest static random access memory (SRAM) to date fits in the space of a single metal-oxide semiconductor (MOS) transistor, according to serial entrepreneur and regular EE Times blogger, Zvi Or-Bach, executive chairman of the newest memory maker in Silicon Valley, Zeno Semiconductor Inc. (Sunnyvale, Calif.). Zeno Semiconductor unveiled its wares at the International Electron Devices Meeting (IEDM) on December 9th.

"The magic," that enables a single NMOS transistor to act as a stable SRAM, according to Or-Bach, "comes from the two intrinsic bipolar N-P-N transistors whose emitters are the n+ material beneath the source and drain with an open base and a common collector in the N-well at the bottom."

Zeno Semiconductor builds its single-transistor static random access memory (SRAM) out of one NMOS transistor containing inside it two intrinsic bipolar transistors with a p-well as open bases, with a buried n-well (BNWL) as collectors and with n+ doped source/drain regions below the gate as emitters. The memory is accessed by bit lines (BL) and source lines (SL) surrounded by shallow trend isolation (STI).

One could argue this a three transistor bit-cell (which would still be quite a feat) but because their elements are "intrinsic" the two bipolar N-P-N transistors with open gates and common collector count at most as "virtual" transistors, and to boot, take up no more die area than the single MOS transistor on which the SRAM bit cell is based. Its really just a clever manipulation of the architecture of the single MOS transistor.

Same vertical NMOS transistor with intrinsic N-P-N bipolar transistors (right diagram) accounting for the bi-stable states for 1 and 0 in a single transistor device forming a complete SRAM in a single NMOS transistor.

No matter which side you argue, there is no arguing that the bit-cells are tiny—just 0.025 square microns when cast in 28 nanometer CMOS compared with the usual 0.127 square microns. Zeno's 28-nanometer SRAM bit cells are even 37 percent smaller than Samsung's 10-nanometer FinFET SRAM bit-cells, which measure 0.040 square microns. They can also be used in either 3-D FinFET or fully-depleted silicon on insulator (FD-SOI) planar fabs while maintaining their tiny size which scales to even smaller sizes—approaching the sub-nanometer range—at more advanced nodes.

Zeno has over 50 granted patents on every aspect of its architecture and operation. Zeno's business model is to license their intellectual property (IP) to anyone for a reasonable fee, the company says.

By: DocMemory
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