As 3D XPoint memory chips move out of research and into the fab, an IM Flash executive gave more details about the novel memory technology, its road map and how hard it is to make.

Intel and Micron announced in July they had defined 3D XPoint as a new memory architecture that fills a gap between DRAM and flash, delivering NAND like density at significantly higher performance and lower latency. “Chalcogenide material and an Ovonyx switch are magic parts of this technology with the original work starting back in the 1960’s,” said Guy Blalock, co-CEO of IM Flash an annual event for chip executives here.

It could take 12-18 months to get XPoint into mass production, Blalock said. He noted several challenges for making those chips as well as 3D NAND devices, both in the works at the joint venture’s Lehi, Utah fab.

“We are swimming through deep water to get to the future enabled by these new products,” Blalock said. Nevertheless he promised XPoint samples are “right around the corner… give the R&D guys a little more time to work out the kinks,” he said.

One downside of the new materials is their potential for cross contamination. To mitigate that threat “you proliferate a lot of process steps for layer over layer deposition with a lot of diffusion and CVD,” Blalock said, confirming speculation that emerged last year.

3D Xpoint uses as many as 100 new materials, raising supply chain issues. “For some we may only have one supplier in one location…many customers will not tolerate this level of risk--they want multiple sources or locations for safety from natural disasters,” he said.

The unique vertical designs of XPoint and 3D NAND require more machines running process steps, cutting fab throughput by an estimated 15%. “We have never seen technology that challenges us at this level of de-rating,” Blalock said.

The extra gear could drive 3-5x increases in capital expenses and space needed, compared to prior new generations of flash. In addition, future generations of XPoint are expected to require more spending and space than upgrades of 3D NAND.

Thus IM Flash is pushing equipment makers to raise system productivity dramatically. To keep fab output neutral, wet processes must leap from handling 180 wafers/hour in 26 square feet of floor space for first generation products to handling a whopping 1,000 w/h in 20 square feet for third generation parts.

“Wet processing equipment is doing wonderful things…[but] dry etch is not moving much of anywhere in productivity to meet the challenge,” Blalock said, calling for 2-3x productivity gains up from traditional 20-30% improvements.

The challenges could impact the road map for XPoint. Blalock foresees a straightforward progression for 3D NAND starting at 32 layers and rising to 48 and 64 layers. XPoint initially will come in a two-layer stacks and “we clearly see four-layer stacks and some benefit from a design shrink with the right lithography…if EUV comes along three generations of 3D XPoint are fairly straightforward,” he said.

In an NVMe-based solid state drive, XPoint chips can deliver more than 95,000 I/O operations per second at a 9 microsecond latency, compared to 13,400 IOPs and 73 ms latency for flash. That should open up a variety of applications from servers running big-data analytics and machine learning to high-end games machines.

The second-generation XPoint could be useful a kind of hybrid main memory with DRAM for applications that would benefit from more density and tolerate higher latency, Blalock suggested.

A version of XPoint in DIMMs will enable up to 6 TBytes main memory in a two-socket Xeon server at about half the cost of DRAM, Diane Bryant, general manager of Intel’s data center group, said in September, suggesting the servers will ship in 2017.

By: DocMemory
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