One area where SRAM is seeing some continued stickiness is the growing automotive segment, as vehicles continue to get smarter and provider more digital information, whether it's to help the driver or entertain the passengers.

The segment also includes autonomous vehicles, something Renesas Electronics Corp. has in mind for its new two-port on-chip SRAM for use in SoCs for in-vehicle infotainment systems. The new on-chip SRAM will be used as video processing buffer memory in high-performance SoCs that will play an important role in making the autonomous-driving vehicles of the future safer and more reliable.

In a telephone interview from Tokyo with EE Times, Koji Nii, chief professional for the Design Platform Business Department within Renesas' 1st Solution Business Unit, said the autonomous vehicle market is fast approaching on the horizon in Japan, as the country has committed to making it possible for highways to accommodate self-driving cars by 2019, followed by downtown city cores in 2022.

Already, advanced driver assistance systems (ADAS) such as automatic braking employing radar or other sensors have become widespread, as well as technology uses video data from vehicle cameras to recognize the peripheral environment and the driver in order to provide accurate information to the driver, said Nii. While Renesas supports a number of electronic systems within vehicles, encompassing MCU and SoC offerings for power train, chassis, in-car networking, safety and security applications, the new SRAM is aimed the infotainment and communication systems of the car, where fast, real-time processing is particularly important, including video.

A large amount of SRAM configured as high-performance internal buffer memory is essential for fast and accurate processing of video data. In addition to increasing the operation speed of the SRAM, said Nii, it's also critical to enable multi-port operation allowing simultaneous read and write accesses, which fetch video processing data for operations and store the data after operations finish.

Renesas has fabricated SRAM prototypes using a 16nm process that achieved a fast read access time of 313 picoseconds at the low voltage of 0.8 V. Nii said ingle-port SRAM cells are used to implement two-port SRAM functionality that allows independent read and write operations, making it possible to achieve fast read access alongside power efficiency and compact chip size.

By: DocMemory
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