Keeping the pace of innovation that has has led to massive gains in computing power will require not only continued improvements in semiconductor process technology but also better integration of system components and improvements in micro-architectural efficiency, power management, memory integration and software, according to Lisa Su, president and CEO of AMD.

In a keynote address at the IEEE International Electron Device Meeting (IEDM) here this week, Su called on the industry to come together to chart a path toward satisfying the huge demand for more computing power to continually improve user experiences and help to solve some of the world's toughest problems.

"The next level of computing power, especially for consumers, is really around immersive computing and the idea that we all have many, many devices connected to us," Su said in a keynote address at the IEEE International Electron Devices Meeting (IEDM).

Su argued in favor of collaboration to move the industry beyond challenges associated with ongoing increasing memory bandwidth latency and cost, power consumption and die sizes. She advocated in favor of multi-chip architectures with efficient die-to-die interconnects with high-performance, scalable links.

Although it is a matter of debate, many believe that the industry has slipped behind the pace of innovation prescribed by Moore's Law, which states the number of transistors per square inch of a chip would double every 18 months. Today, according to Su, it takes about 2.4 years to double the density of transistors per square inch. In addition, increasing die sizes are becoming economically problematic, memory bandwidth has become less efficient over time and the power consumption of SoCs is increasing by about 7 percent per year, Su said.

In high-performance computing, the semiconductor industry has continued to deliver consistent and exponential CPU and GPU performance gains, doubling performance-per-watt ratio every 2.4 years, Su said. She estimated that about 40 percent of this performance gain is attributable to process technology improvements.

"It's incredibly important for us to do the work on the architecture and systems side, and frankly there are a lot of opportunities for us to move forward in that domain," Su said.

In addition to multi-chip architectures, Su spotlighted 3D stacking, memory integration and power management as areas ripe with opportunities to boost performance and improve computational efficiency.

Su began her address by saying that it was an honor for her to be speaking at the conference 25 years after receiving an award for best student paper at IEDM in 1992 at the age of 22.

In an interview with EE Times following the keynote address, Su — who ascended to AMD's helm three years ago after years in engineering and R&D positions at AMD, Freescale and IBM — said though she has been away from deep R&D for some time, putting together the presentation for IEDM was enjoyable.

"IEDM is really the premier semiconductor devices conference," Su said. "For Ph.D students and a lot of the key industry, it attracts the best and the brightest to really talk about what the latest and greatest trends are."

By: DocMemory
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