Continuing to move fast in multiple directions at once, TSMC announced that it is in volume production with a 7-nm process and will have a version using extreme ultraviolet (EUV) lithography ramping early next year. In addition, it gave its first timeline for a 5-nm node and announced a half-dozen new packaging options.

Meanwhile, the foundry is pushing power consumption and leakage down on more mainstream 22-/12-nm nodes, advancing a laundry list of specialty processes and rolling out an alphabet soup of embedded memories. At the same time, it is exploring future transistor structures and materials.

Overall, the Taiwanese giant expects to make 12 million wafers this year with R&D and capex spending both on the rise. It has even started production of 16-nm FinFET chips in Nanjing, a big first for China.

The only bad news is that the new process nodes are partial steps delivering thinner gains. The new normal is for performance increases and power reductions that generally fall in a 10% to 20% range, a reality that makes the new packaging and specialty processes increasingly important.

TSMC is in volume production of 7-nm chips today with more than 50 tapeouts expected this year. It’s making CPUs, GPUs, AI accelerators, cryptocurrency mining ASICs, networking, gaming, 5G, and automotive chips.

The node delivers 35% more speed or uses 65% less power and sports a 3x gain in routed gate density compared to the 16FF+ generation two steps before it. By contrast, the N7+ node with EUV will only deliver 20% more density, 10% less power, and apparently no speed gains — and those advances require use of new standard cells.

TSMC has validated in silicon what it calls foundation IP for N7+. However, several key blocks will not be ready until late this year or early next year, including 28–112G serdes, embedded FPGAs, HBM2, and DDR5 interfaces.

Expect 10% to 20% more effort laying out IP for the EUV process, said Cliff Hou, vice president of R&D for design and technology platforms. “We developed a utility to migrate IP with incremental effort.”

Fully certified EDA flows for N7+ will be ready by August. Meanwhile, yields of a test 256-Mbit SRAM at N7+ are as good as yields were for the early 7-nm node, he said.

Looking ahead, TSMC aims to start risk production of a 5-nm node in the first half of 2019, focusing on mobile and high-performance computing chips.

Compared to the initial 7 nm without EUV, the 5-nm node promises a 1.8x greater density than 7 nm. However, it is only expected to reduce power by up to 20% or raise speeds by about 15%, perhaps 25% using Extremely Low Threshold Voltage (ELTV), details of which TSMC has not yet provided.

“Without EUV, they can’t deliver the same scaling advantage as past nodes,” said Mike Demler, an analyst with the Linley Group. “If you look at N7+, they claim an additional 20% scaling over N7. So EUV is required to get closer to traditional Moore’s Law scaling. Their N5–N7 scaling just gets worse.”

By: DocMemory
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