In 25 years, after Facebook, Google, and Amazon have marched toward global domination by designing their own chips, what will the semiconductor industry look like? In a way, we’ve seen that future, and it’s here. Big data analysis, artificial intelligence, augmented and virtual reality, and autonomous vehicles have already emerged, although not yet in perfect form.

Nonetheless, most chip designers can’t even imagine that brave new world, let alone the inventions that they must fashion to stay relevant. A question that haunts designers is the sheer uncertainty of the industry’s direction. As Moore’s Law nears its “economic dead end” for most chip vendors (except giants like Intel and Samsung), is there somewhere else to turn?

In July 2016, the Semiconductor Industry Association scrapped a technology plan widely known within the industry as the International Technology Roadmap for Semiconductors (ITRS). SIA’s decision to end the ITRS illustrated the industry’s admission that Moore’s Law is not just slowing down. The industry needs new tools, charts, and programs to define research gaps between where it has been and where to go in an even more connected world.

This is where Nicky Lu, Chairman, CEO, and Founder of Taiwan’s Etron Technology, comes in.

Lu has long advocated “heterogeneous integration” (HI). He promotes the idea that the semiconductor industry must, at last, outgrow its obsession with pitch shrinkage. To push growth, it must go creative with the “heterogeneous integration of different technologies.” By HI, he does not mean homogeneously integrated SoCs, Systems-in-Package (SiPs), or Multi-Chip Modules (MCMs). Lu views HI as “a holistically integrated approach” that involves system design, algorithms, and software, together with different types of silicon dice such as SoC, DRAM, flashes, A-to-D/D-to-A, power management, security, and reliability control dices.

Thus far, the chip industry has made great progress in SiP. However, Lu told us, “Now in 2018, I am seeing [the need for] even more sophisticated HI that actually integrates not only silicon dice but also non-silicon materials.”

The groundwork to develop a Heterogeneous Integration Roadmap (HIR) began in 2015, when the SIA and one of the IEEE Societies signed an MOU, according to Bill Bottoms, chairman of Third Millennium Test Solutions (3MTS). Bottoms is a co-chair of HIR, along William Chen, ASE Fellow at ASE Group.

By 2016, HIR got official sponsorships from three IEEE Societies: the IEEE Electronics Packaging Society (EPS), IEEE Electronic Devices Society (EDS), and IEEE Photonics Society. Semiconductor Equipment and Materials International (SEMI) and the American Society of Mechanical Engineers (ASME)’ Electronic and Photonic Packaging Division (EPPD) also signed up to work on HIR.

The wheels really started to churn last year. As the HIR group held workshops throughout the world to evangelize its mission, “close to 1,000 scientists, researchers, and senior engineers showed up and pledged to participate in HIR,” said Bottoms. When it comes to its membership, “We are keeping the quality of standards very high,” he stressed. “We are picking only those with technical credentials and real commitment to contribute to each technical working group.” Typical marketing onlookers who just want to suck up information aren’t included, explained Bottoms.

Bottoms defines the scope of the HIR as “identification of the difficult challenges we need to overcome in meeting technical requirements for the next 15 years and 25 years for emerging research areas.” The group is developing a “pre-competitive” roadmap, he noted. It’s far more efficient in pooling industry resources to chart the future instead of fragmenting efforts and diverging into too many directions. The HIR group sees the primary integration technology for potential solutions as “complex SiP architectures.”

In many ways, Bottoms said that the industry has begun to see products in which silicon dice and non-silicon materials are together in one package. “One good example of HI is Intel’s photonics optical transceivers,” he noted, in which Intel applied silicon wafer planar manufacturing technology to the volume manufacture of electro-optical transceivers.

Another example is what’s known as “S2,” the second-generation SiP in the Apple Watch 2. Just like S1, these SiP modules mix package styles in one module. The module contains components that can be packaged as bare-die (CSP, WLP, etc.) or traditional wire-bonded packages, or even multi-chip configurations like package-on-package or a multi-die memory DRAM or NAND. “Apple has pushed the SiP concept so far out into the future — a road nobody has taken before,” said Bottoms. TechInsights, in its Apple Watch 2 teardown, wrote, “The S2 contains more than 42 die! That is a lot of silicon in such a small module.” Similarly, Bottoms was marveled at the 98 interconnects inside S2.

Nothing pleases Lu more than the growing momentum behind HI. Heterogeneous integration is no longer just his passion, but is spreading throughout electronics, Lu told us.

Earlier this year, Lu gave a plenary talk entitled “Synergistic Growth of AI and Silicon Age 4.0 through Heterogeneous Integration of Technologies” at an IEEE-organized event in Santa Clara. He told us, “So many people came to see me after my speech. They were all so excited.”

What’s so exciting? Lu’s talk wasn’t about the nuts and bolts of integrating heterogeneously. Instead, he described his focus as broadening the scope of research and development in the semiconductor industry.

Now that the chip industry is no longer hostage to continuous scaling, Lu believes that it can apply its knowledge to a larger mission. The next step, he says, is “pervasive intelligence” enabled across different industries ranging from AI, human, and natural interface to bio, cells, bacteria, and medical intelligence.

It’s one thing to discuss best designs for next-generation AI chips. Everyone does. But if the industry wants a “roadmap” to extend forward 25 years, it’d better start making intelligence pervasive, explained Lu.

Before describing what Lu defines as “pervasive intelligence,” it’s important to understand how Lu’s interest in heterogeneous integration has evolved.

Born and educated in Taiwan, Lu earned his M.S. and Ph.D. in Electrical Engineering from Stanford University. At the IBM Research Div., where he started his career, he’s known as a co-inventor of a 3D-DRAM technology and a designer of High-Speed CMOS DRAM (HSDRAM).

Over several decades, this technical virtuosity, abetted by an infectious smile and passionate demeanor, have made Lu a vocal force within the semiconductor industry.

Lu has advocated Heterogeneous Integration ever since delivering a plenary talk at the 2004 International Solid-State Circuits Conference (ISSCC). He pointed out that “future system chips will fully utilize multi-dimensional integration, within a single package, of multiple dies that cover a variety of digital, analog, memory, and RF functions and technologies.”

Lu’s prediction of an emerging era of 3D ICs was considered bold then. He wanted to demonstrate what could be accomplished by the vertical integration of dice at a time when the chip world was largely content to follow Moore’s Law — whose sole precept is the constant scaling of transistors.

Fast forward to 2018, when it’s fair to argue that the era of the SiP is already here and the death of Moore’s Law is greatly exaggerated.

The packaging technology that the chip industry knew in 2004 has made remarkable strides. Consider the integrated fan-out (InFO) wafer-level packaging technology achieved by the Taiwan Semiconductor Manufacturing Co. TSMC’s InFO enabled Apple to offer a very thin package-on-package, with a high number of I/O pads and better thermal management for the A10 applications processor in the iPhone 7.

By: DocMemory
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