Others are taking the string-stacking approach. In a 64-layer device, for example, some developed two separate 32-layer parts. Then, they stacked one on top of the other, enabling a 64-layer chip.

Then, for 96 layers, some combine two separate 48-layer chips. In both cases, the two chips are separated by an insulating layer.

Both approaches, single deck and string stacking, are viable. “Double stacks are probably becoming more of the norm at 96. There might be some doing single stacks,” said Mahendra Pakala, managing director of process development at Applied Materials.

Each approach has some technical and cost issues. In string stacking, for example, a vendor is making two devices. In effect, the vendor is doubling the number of steps to make a single device, which translates into cost and cycle time.

In the single-deck approach, a vendor is making a single device in one shot. This, in theory, reduces cost and cycle time. But in the fab, the single-deck approach is difficult. Some believe this approach may run out of steam over time.

Both approaches follow the same process steps. In the fab, 3D NAND is different from planar NAND. In 2D NAND, the process is dependent on shrinking the dimensions using lithography.

Lithography is still used for 3D NAND, but it isn’t the most critical step. So for 3D NAND, the challenges shift from lithography to deposition and etch.

The 3D NAND flow starts with a substrate. Then, vendors undergo the first challenge in the flow—alternating stack deposition. Using chemical vapor deposition (CVD), the process involves depositing and stacking alternating thin films on the substrate.

First, a layer of material is deposited on the substrate, followed by another layer on top. The process is repeated several times until a given device has the desired number of layers.

Each vendor uses different materials. For example, Samsung deposits alternating layers of silicon nitride and silicon dioxide on the substrate. “You deposit oxide-nitride or oxide-poly, depending on the kind of device you are fabricating,” Lam’s Gottscho said during the presentation.

It’s possible to stack hundreds of layers on the substrate. But as more layers are added, the challenge is to stack the layers with the exact thickness and good uniformities at high throughputs. The big challenges are stress and defect control. In addition, the stack tends to bow under stress.

Film stack deposition challenges. Source: Lam Research.

That becomes more apparent in the single-deck approach. For this, the supplier would stack 96 layers of films on the substrate. “That’s a lot of deposition. If you look at any other device, such as traditional DRAM devices, logic devices or previous 2D NAND flash, they didn’t have 96 layers of deposited films,” Gottscho said.

There are solutions. For example, Lam has released a product that performs backside deposition, which compensates for front-side stress.

Another way to avoid stress is to use string stacking. For example, you deposit the layers on one 48-layer device, and then repeat the process on the other device, forming a 96-layer product.

Generally, a 48-layer alternating stack deposition process is mature and produces relatively less stress, but there are challenges. “You need to get one deck lined up with the other. If they both are highly deformed, you are going to have big alignment errors,” Gottscho said.

High-aspect ratio etch

Following this step, a hard mask is applied on the film stack and holes are patterned on the top. Then, here comes the hardest part of the flow—high-aspect ratio (HAR) etch.

For this, the etch tool must drill tiny circular holes or channels from the top of the device stack to the bottom substrate. The channels enable the cells to connect with one another in the vertical stack. A device may have 2.5 million tiny channels in the same chip. Each channel must be parallel and uniform.

This step is performed using today’s reactive ion etch (RIE) systems. In simple terms, the etcher creates tiny channels by bombarding the surface with ions. “That etch is very difficult and very time-consuming,” Lam’s Gottscho said. “There’s a fundamental law of aspect ratio scaling in etching that says the higher the aspect ratio, which is the deck of the deposited layers and the smaller the hole, the slower the etch.”

Then, as the etch process penetrates deeper into the channels, the number of ions may decrease. This slows down the etch rate. Even worse, unwanted CD variations may occur.

Channel etch challenges. Source: Lam Research.

A 64-layer device has an aspect ratio of 60:1, compared to 40:1 for a 32-/48-layer device. Still, today’s etchers can do the job, at least up to a point. “The 32-, 48- and 64-layer devices use conventional etching tools for the HAR channel hole,” TechInsights’ Choe said.

Based on this premise, it’s conceivable that suppliers can migrate from 96 to 128 layers and beyond using string stacking. In theory, using traditional etch tools, a vendor could process two 64-layer devices, enabling 128 layers.

The single-deck approach is another story, as aspect ratios climb beyond 70:1. “For 96 layers, we can etch with a one-step etch. But you might have etch damage or the profiles are not good. If we use one-step etching, that’s quite difficult,” Choe said.

For a single-deck 96-layer device and beyond, the industry requires traditional etch tools for the HAR step. “However, another plasma tool and methods are needed. Cryogenic etching is an example,” Choe said.

Traditional etchers involve a process of alternating etch and passivation steps at room temperature. In contrast, cryogenic etching is conducted at cryogenic temperatures. They use fluorine-based high-density plasmas.

“Cryogenic etch is not new. People have used it for other applications,” Applied’s Pakala said. “Atoms move around at high temperatures. If you don’t want the atoms while etching, you reduce the temperatures.”

Cryogenic etching is difficult and expensive, however. “We are back to the future. What we’re doing is introducing cryogenic etching. It’s been in the literature since the mid-1980s, but it was very much ahead of its time,” Lam’s Gottscho said. “It’s a difficult technology, but we’ve made great progress. The advantage of cryogenic etching is that you get more reactants down at the etch front at the bottom of this high aspect ratio feature. That enhances the etch rate. That’s an expensive technology to implement, but the benefits outweigh those added costs.”

More steps

Following the process, each vendor follows a different flow. In some flows, the channel is lined with polysilicon and filled with silicon dioxide.

Then, the original nitride layers in the stack are removed. A gate dielectric is deposited, followed by a conductive metal gate fill using tungsten for the wordlines. That’s a simplified version of a complex process.

Generally, this entire process is conducted in one continuous flow in the fab. A vendor will first take a substrate and build logic circuitry on top of it, followed by the NAND structure.

YMTC, however, has another approach. The company processes the circuitry on one wafer and the NAND structure on another wafer. Then, the two wafers are bonded and connected electrically using millions of metal vertical interconnect access structures. YMTC’s approach, dubbed Xtacking, reduces the manufacturing cycle time by 20% and allows for higher bit density.

It will take time before YMTC ramps up and moves into production, so the incumbent players will continue to dominant the competitive landscape for the foreseeable future.

To be sure, though, it’s a good time for OEMs. 3D NAND products will be plentiful at competitive prices.

By: DocMemory
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