TSMC taped out its first chip in a process making limited use of extreme ultraviolet lithography and will start risk production in April on a 5-nm node with full EUV. Separately, the foundry forged partnerships with four partners to support online services for back-end chip design.

The foundry’s update showed that area and power gains continue in its leading-edge nodes, but chip speeds are no longer advancing at their historic rate. To compensate, TSMC gave an update on a half-dozen packaging techniques that it is developing to speed connections between chips.

Backers say that cloud-based services will shorten the time and extend the reach of chip design tools, helping expand a semiconductor industry facing the slowdown of Moore’s Law. However, they note that cloud design is still in an early phase that typically requires setting up and optimizing custom sites.

In process technology, TSMC announced that it taped out a customer chip in an N7+ node that can use EUV on up to four layers. Its N5 that will use EUV on up to 14 layers will be ready for risk production in April. EUV aims to lower costs by reducing the number of masks required for leading-edge designs.

Rival Samsung is ramping a 7-nm node using EUV. Intel is not expected to use EUV anytime soon, according to analysts. Globalfoundries announced in August that it has halted work on 7 nm and EUV.

TSMC said that N5 will deliver 14.7% to 17.7% speed gains and 1.8 to 1.86 area shrinks based on tests with Arm A72 cores. The N7+ node can deliver 6% to 12% less power and 20% better density; however, TSMC did not mention speed gains.

Chip designs for the N5 node can start today, although most EDA tools won’t hit a 0.9-version readiness until November. Many of TSMC’s foundation IP blocks are ready for N5, but some, including PCIe Gen 4 and USB 3.1, may not be ready until June.

The N7+ node sports a tighter metal pitch and includes a single-fin library that can help lower dynamic power. It will be available in a version for automotive designs by April. N7+ offers “nearly the same analog performance as N7,” said Cliff Hou, vice president of technology development at TSMC.

Transistor density at N7 is 16.8x greater than at the foundry’s 40-nm node, said TSMC. Unfortunately, costs are increasing, too. One source pegged total costs for an N5 design including labor and licensing at $200 to $250 million, up from $150 million for a 7-nm chip today, limiting pursuit of Moore’s Law to the well-heeled.

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