Weapon complexity and the attendant costs along with a shortage of weapon test ranges are forcing military planners to rely more heavily on simulators to train soldiers and pilots. Those requirements along with the rise of AI-enable technologies have highlighted the need for more computing horsepower to simulate the electronic battlefield with greater fidelity.

As part of its Electronic Resurgence Initiative, the Defense Advanced Research Projects Agency (DARPA) has launched a simulator initiative that will harness high-performance computing to support training on the digital battlefield. Among the goals of the Digital RF Battlespace Emulator program are balancing the computational performance of graphics processors with the low latency of FPGAs to achieve “real-time HPC.”

The result would be “high-fidelity emulation of RF environments” characterized by multifunction radars and antennas used for electronic warfare, secure communications and other situational awareness.

DARPA said the simulation and training push will advance real-time supercomputing that would support the new RF test range. At the processor level, program managers said the initiative will seek to forge a new HPC architecture and “domain-specific hardware accelerators” that combine the processing power of GPUs and the low- latency attributes of FPGAs.

Tools, specifications and interfaces also would be developed to support integration of the resulting real-time HPC platform that would serve as the processing engine for the virtual RF test range. The components would also be used to run test scenarios while linking the real-time simulator with external training resources.

The result would be the “world’s first large-scale virtual RF test range,” asserted Paul Tilghman, program manager for DARPA’s Microsystems Technology Office. “Existing computing technologies are unable to accurately model the scale, waveform interactions or bandwidth demands required to replicate real-world RF environments,” Tilghman added.

The agency recently held a “Proposers’ Day” to gather industry input on the virtual test bed. The effort represents the next phase of the DARPA’s $1.5 billion Electronics Resurgence Initiative designed to move processor technology beyond Moore’s Law scaling. The second phase of the chip initiative is focusing on specific applications. In the case of the real-time HPC simulator, DARPA said the goals include “bringing the benefits of domain specific processing architectures to defense systems.”

By: DocMemory
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