sureCore, the Sheffield low-power SRAM IP specialist, says its PowerMiser low power SRAM IP is now available for designs targeting the Samsung 28nm FDS process.

“As the low power IC design and SRAM IP standard products leader, we’re responding to more and more enquiries about the low power consumption capabilities of silicon-on-insulator technology,” says CEO Paul Wells.

Making PowerMiser available on Samsung’s 28nm FDS technology responds to demands for low power devices, particularly those powering IoT, wearable, and medical applications.”

At the 28FDS process node, the single port PowerMiser supports a wide operating voltage range from 0.7V to 1.2V and demonstrates 50% dynamic and 20% leakage power savings of competitive offerings, depending on operating conditions.

On-chip BIST and Byte Write capability, a key requirement for many embedded microcontroller designs, are also provided.

The compiler utilizes sureCore’s patented, innovative microarchitecture techniques supporting single instance capacities to 576Kbit with word lengths of up to 144bits with three mux factors; 4, 8 and 16. It allows designers to trade-off between various memory sizes in terms of mux factor, depth, word length and local bit line length.

It automatically generates datasheets, simulation model (Verilog), layout (LEF) and timing/power (Liberty) models to enable standard EDA tool flows.

The patented PowerMiser “Bit Line Voltage Control” technique virtually eliminates performance compromises at low operating voltages. Retentive sleep modes, including light sleep for rapid wake-up as well as deep-sleep for maximal leakage current savings, are also featured.

By: DocMemory
Copyright © 2023 CST, Inc. All Rights Reserved