Intel is sampling Stratix 10 FPGAs which have 10.2 million logic elements.

The FPGA uses Intel’s Embedded Multi-die Interconnect Bridge (EMIB) technology.

EMIB technology stitches two Stratix 10 GX FPGA core fabric die (with a capacity of 5.1 million logic elements per die) along with appropriate I/O tiles.

The chip is targeted at the ASIC prototyping and emulation market.

The Stratix 10 GX 10M FPGA is the first Intel FPGA to use EMIB to logically and electrically bond two FPGA fabric die together. Previously, Intel has used EMIB technology to connect I/O and memory tiles to FPGA die.

For example, Intel Stratix 10 MX devices incorporate either 8 or 16 Gbytes of EMIB-connected, 3D stacked HBM2 SRAM tiles. The Intel Stratix 10 DX FPGA incorporates EMIB-connected P tiles that provide PCIe 4.0 compatibility.

The P tile used in the Intel Stratix 10 DX FPGA is the first component-level device to appear on the PCI-SIG System Integrators List for PCIe 4.0. The same P tile is also integrated into the Intel Agilex FPGA to deliver PCIe 4.0.

By: DocMemory
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