Friday, January 24, 2020
Several foundries are ramping up their new 5nm processes in the market, but now customers must decide whether to design their next chips around the current transistor type or move to a different one at 3nm and beyond.
The decision involves the move to extend today’s finFETs to 3nm, or to implement a new technology called gate-all-around FETs (GAA FETs) at 3nm or 2nm. An evolutionary step from finFETs, gate-all-around provides better performance, but these new transistors are difficult to make, expensive, and the migration could be painful. On the plus side, the industry is developing new etch, patterning and other technologies to help pave the way towards these nodes.
Rollout schedules for these GAA FETs vary by foundry. Samsung and TSMC are both in production at 7nm with finFETs, and they will ramp up 5nm using finFETs later this year, along with various half-node offerings around 5nm. These processes will provide both speed and power improvements.
At 3nm, though, Samsung plans to jump to nanosheet FETs, a type of GAA transistor, sometime next year or in 2022. TSMC, meanwhile, plans to first introduce finFETs at 3nm. Then, TSMC will introduce GAA in the latter stages of 3nm or 2nm, according to multiple analysts and equipment vendors.
“TSMC is accelerating 3nm finFETs, which is a shrink of 5nm,” said Handel Jones, chief executive of IBS. “Risk production for TSMC’s 3nm finFETs is 2020. Initial volume production is slated for Q3 2021, one quarter ahead of Samsung’s 3nm launch. TSMC’s gate-all-around developments are lagging Samsung by 12 to 18 months. But TSMC’s aggressive 3nm finFET strategy may compensate for the lag time.”
TSMC continues to evaluate its 3nm options, however, and its plans could change. The company, which declined to elaborate, will disclose its 3nm plans soon. Nonetheless, TSMC’s move to extend finFETs to 3nm is a logical step. Moving to a new transistor could create potential disruptions for customers. But eventually, finFETs will run out of steam, so TSMC has no choice but to migrate to gate-all-around.
Others are also developing advanced processes. Intel, a bit player in the commercial foundry business, is shipping 10nm with 7nm in R&D. (Intel’s 10nm is similar to 7nm from the foundries.) Meanwhile, SMIC is ramping up 16nm/12nm finFETs with 10nm/7nm in R&D.
All advanced processes are expensive, and not all chips require 3nm or other advanced processes. In fact, escalating costs are prompting many to explore other options. Another way to get the benefits of scaling is by putting advanced chips in a package. Several companies are developing new, advanced package types.
Is scaling over?
A chip consists of three parts—transistor, contacts and interconnects. The transistor serves as the switch in a device. Advanced chips have as many as 35 billion transistors.
The interconnects, which reside on the top of the transistor, consist of tiny copper wiring schemes that transfer electrical signals from one transistor to another. The transistor and interconnect are connected by a layer called the middle-of-line (MOL). The MOL consists of tiny contact structures.
IC scaling, the traditional way of advancing a design, shrinks the transistor specs at each process node and packs them onto a monolithic die.
For this, chipmakers every 18 to 24 months introduced a new process technology with more transistor density. Each process was (and still is) given a numerical node name. Originally, the node name was tied to the transistor gate length dimensions.
At each node, chipmakers scaled the transistor specs by 0.7X, enabling the industry to deliver a 40% performance boost for the same amount of power and a 50% reduction in area. Chip scaling enables new electronic products with more functions.
The formula worked as chipmakers marched down various process nodes. But a big change occurred at 20nm, when traditional planar transistors ran out of steam. Starting in 2011, chipmakers migrated to finFETs, enabling them to scale their devices.
However, finFETs are more expensive to manufacture. As a result, process R&D costs have skyrocketed. So now the cadence for a fully scaled node has extended from 18 to 30 months, or even longer.
At advanced nodes, Intel followed the 0.7X scaling trend. But starting at 16nm/14nm, others deviated from the formula, creating some confusion in the market.
At that point, the node names became fuzzy and were no longer tied to any transistor spec. Today, the node names are little more than marketing terms. “The node designation is becoming more misleading and meaningless,” said Samuel Wang, an analyst at Gartner. “For example, at 5nm or 3nm, there is no single geometry that is actually 5nm or 3nm. Plus, the process commonality decreases widely between vendors. For the same node, the performance differs from TSMC to Samsung and of course versus Intel.”
Scaling is also slowing at advanced nodes. Generally, a 7nm foundry process consists of a contacted poly pitch (CPP) ranging from 56nm-57nm with a 40nm metal pitch, according to IC Knowledge and TEL. At 5nm, the CPP is roughly 45nm-50nm with a 26nm metal pitch. CPP, a key transistor metric, measures the distance between a source and drain contact.
Plus, the price/performance benefits are no longer following the same curve, prompting many to say that Moore’s Law has run its course.
“Moore’s Law is not really a law, but an observation that became a self-fulfilling prophecy to keep the semiconductor business moving forward. The economic aspect of Moore’s Law began to decline with the increase in cost of multiple patterning and EUV,” said Douglas Guerrero, senior technologist at Brewer Science. “Increases in computing power will come in new designs and architectures, but this is not scaling. That means future chips will increase in computing power, but the cost will not necessarily go down at the same rate as in the past.”
Scaling isn’t exactly going away. AI, servers and smartphones are driving the need for faster chips at advanced nodes. “A decade ago, some were saying, ‘Who needs more transistors?’ Some also thought the world was out of ideas for what to do with faster computing other than exotic applications,” said Aki Fujimura, chief executive of D2S. “Today, for IoT, lower cost with good-enough performance and integration wins over more and higher compute density. But faster transistors are needed to make faster and lower power chips that have more transistors per dollar.”
Clearly, not all require advanced nodes. Demand is strong for chips at mature processes. “These product rollouts include RF ICs and OLED driver ICs found in 5G smartphones, and power management ICs designed into computing and solid-state drive applications,” said Jason Wang, co-president of UMC, in a recent conference call.
In chip scaling, meanwhile, chipmakers for years followed the same process roadmap with an identical transistor type. In 2011, Intel moved to finFETs at 22nm, followed by the foundries at 16nm/14nm.
In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin. A finFET has two to four fins. Each fin has a distinct width, height and shape.
Intel’s first-generation finFETs at 22nm had a fin pitch of 60nm and a fin height of 34nm. Then, at 14nm, Intel’s finFETs had both a 42nm fin pitch and height.
So Intel made the fins taller and thinner to scale the finFET. “FinFET scaling reduces lateral dimensions to increase device density per unit area while increasing fin height as a way to improve device performance,” said Nerissa Draeger, director of university engagements at Lam Research, in a blog.
At 10nm/7nm, chipmakers followed the same path to scale finFETs. In 2018, TSMC shipped the first 7nm finFET process, followed by Samsung. Meanwhile, Intel last year shipped 10nm after several delays.
In 2020, the competition will intensify in the foundry business. Samsung and TSMC are ramping up 5nm and various half-nodes offerings. 3nm is in R&D.
All processes are expensive. The design cost for a 3nm chip is $650 million, compared to $436.3 million for a 5nm device, and $222.3 million for 7nm, according to IBS. These are “mainstream design costs,” which means one year after a given technology has moved into production.
Compared to 7nm, Samsung’s 5nm finFET technology provides up to a 25% increase in logic area with 20% lower power or 10% higher performance.
In comparison, TSMC’s 5nm finFET process “offers 15% faster speed at same power or a 30% power reduction at same speed with 1.84X logic density of the 7nm node,” said Geoffrey Yeap, senior director of advanced technology at TSMC, in a paper at the recent IEDM conference.
Chipmakers made some big changes at 7nm and 5nm. To pattern the critical features in chips, the two companies made the transition from traditional 193nm lithography to extreme ultraviolet (EUV) lithography. Using a 13.5nm wavelength, EUV simplifies the process.
EUV doesn’t solve all challenges in chip scaling. “Solving those challenges requires multiple techniques that extend beyond scaling to include the use of new materials, new types of embedded nonvolatile memories and advanced logic architectures, new approaches to deposition and etch, and innovations in packaging and chiplet design,” said Regina Freed, managing director of patterning technology at Applied Materials, in a blog.
Behind the scenes, meanwhile, Samsung and TSMC are readying their 3nm processes. In the past, chipmakers followed the same path, but this is where vendors are diverging, according to today’s roadmaps.
“3nm could come in several different options, such as finFETs and gate-all-around,” Garner’s Wang said. “This offers a different combination of cost, density, power and performance for customers to choose from in fitting their special needs.”
As stated, Samsung will introduce nanosheet FETs at 3nm. TSMC is also working on them, but it plans to extend finFETs for another generation. “TSMC will have 3nm finFETs in Q3 2021,” IBS’ Jones said. “TSMC’s gate-all-around will be around 2022 or 2023.”
This is where foundry customers must weigh an assortment of cost and technical tradeoffs. Extending the finFET is a safer path. “Many customers consider TSMC to be a low risk vendor here,” Jones said.
Nevertheless, gate-all-around provides more performance to some degree. “3nm gate-all-around has a lower threshold voltage and potentially a 15% to 20% power reduction compared with 3nm finFETs,” Jones said. “But the performance difference is likely to be under 8% because the MOL and the BEOL are the same.”
The backend-of-the-line (BEOL) and MOL are the bottlenecks in advanced chips. Contact resistance is an issue in the MOL.
The BEOL is where the copper interconnects are made in chips. The interconnects are becoming more compact at each node, causing resistance-capacitance (RC) delays in chips. FinFETs and gate-all-around are different transistor types, but they likely will have similar copper interconnect schemes at 3nm. RC delay will be an issue for both transistors.
There are other challenges. FinFETs will run out of steam when the fin width reaches 5nm. 5nm/3nm finFETs are bumping up against these limits.
Plus, a 3nm finFET may consist of one fin, compared to two or more fins for other nodes. “The single fin must have enough drivability. To extend the finFET to N3, we need a special technique to enhance the single fin power and/or reduce backend parasitics,” said Naoto Horiguchi, director of CMOS device technology at Imec.
One way to extend the finFET to 3nm is to move to germanium materials for the p channel. A 3nm finFET with high-mobility channels will provide a performance boost, but there are some integration challenges.
Moving to nanosheets
Eventually, finFETs will stop scaling, prompting chipmakers to move to a new transistor, namely nanosheet FETs or related types.
The momentum for nanosheet FETs started in 2017, when Samsung introduced its Multi Bridge Channel FET (MBCFET) for 3nm. The MBCFET is a nanosheet FET. Risk production starts later this year with volume production slated for 2022.
TSMC also is working on nanosheets. In R&D for years, a nanosheet FET is one type of gate-all-around transistor. A nanosheet provides a modest scaling boost over 5nm finFETs, but nanosheets have some advantages.
A nanosheet FET is basically a finFET on its side with a gate wrapped around it. A nanosheet consists of several separate and thin horizontal pieces or sheets, which are vertically stacked. Each sheet makes up a channel.
A gate surrounds each sheet, creating a gate-all-around transistor. In theory, nanosheet FETs provide more performance with less leakage, because the control of the current is accomplished on four sides of the structure.
Initially, nanosheets will have four or so sheets. “A typical nanosheet width is 12nm to 16nm, and the thickness is 5nm,” Imec’s Horiguchi said.
That’s where nanosheets differ from finFETs. FinFETs are quantized with a limited number of fins, which presents some limitations for designers. “The advantage with a nanosheet is that it could have different nanosheet widths. According to the designers’ needs, they can have different widths per device. That gives some freedom for designers. They can find a better sweet spot for performance and power,” Horiguchi said.
For example, a transistor with a wider sheet will have more drive current. A narrow sheet enables a smaller device with less drive current.
A nanosheet is related to a nanowire. Instead of sheets, wires make up the channels. The channel width is limited, which translates into less drive current.
That’s why nanosheet FETs are gaining steam. But there are several challenges for this technology and finFETs at or around 3nm. “The finFET challenges are the quantum control of the fin width and fin profile in a scaled gate length. The nanosheet challenges are n/p imbalance, bottom sheet effectiveness, inter spacer, gate length control and device coverage,” said Jin Cai, deputy director at TSMC, during a presentation at IEDM. (At IEDM, Cai gave a tutorial on 3nm and beyond technologies. Cai didn’t endorse a technology, nor did he disclose TSMC’s plans.)
these challenges in mind, nanosheet FETs will take time to ramp up. “There are many challenges to move to new transistor architectures,” Brewer Science’s Guerrero said. “New materials will certainly be required.”
In a simple process flow, a nanosheet FET starts with the formation of a super-lattice structure on a substrate. An epitaxial tool deposits alternating layers of silicon-germanium (SiGe) and silicon on the substrate. At a minimum, a stack would consist of three layers of SiGe and three layers of silicon.
Then, vertical fins are formed in the super-lattice structure using patterning and etch. Precise CD control is required for the super-lattice structure and fin formation.
Then comes one of the harder steps — the formation of the inner spacers. First, the outer portions of SiGe layers in the super-lattice structure are recessed. This creates small spaces, which are filled with dielectric materials. “Inner spacers are needed to reduce gate to source/drain capacitance,” TSMC’s Cai said. “The inner spacer process control is very critical.”
There are solutions. IBM and TEL recently described a new etch technique for both the inner spacer and channel release processes. This involves an isotropic SiGe dry etch technique with a 150:1 ratio.
This technology enables precise inner spacers. “The indentation of SiGe requires a highly selective lateral ‘blind’ etch of the sacrificial SiGe layers,” said Nicolas Loubet, an R&D manager at IBM, in the paper.
Then, the source/drain are formed. After that, the SiGe layers in the super-lattice structure are removed using an etch process. What’s left are silicon-based layers or sheets, which make up the channels.
High-k/metal-gate materials are deposited in the structure. And finally, the MOL and copper interconnects are formed, resulting in a nanosheet.
That’s a simplified description of this complex process. Nonetheless, as with any new technology, nanosheets may be prone to defects. This requires more inspection and metrology steps in the fab.
“Like the previous architecture transitions we’ve worked on, we are seeing new inspection and metrology challenges with nanosheets,” said Chet Lenox, director of process control solutions at KLA. “On the inspection side, there are a number of new buried defect modes that can be generated with both the inner spacer and nanosheet release. For metrology, IC manufacturers need accurate measurements of individual nanosheets, not just an average of each stack, to help reduce their process variability.”
It also requires new techniques. For example, Imec and Applied Materials recently presented a paper on a scalpel scanning spreading resistance microscopy (s-SSRM) technique for gate-all-around. In s-SSRM, a tiny scalpel cleaves a small portion of the structure. This provides a cross-section to enable dopant profiles.
In R&D, Imec is developing more advanced forms of gate-all-around, such as CFETs and forksheet FETs, which are targeted for 2nm and beyond.
By then, IC scaling could be too expensive for most, particularly in light of diminishing power and performance benefits. This is why advanced packaging is becoming more appealing. Instead of cramming all chip functions on the same die, the idea is to break up the device into smaller dies and integrate them in an advanced package.
“This certainly depends on the applications,” said Rich Rice, senior vice president of business development at ASE. “We are definitely seeing more of that activity even down in the deep sub-micron nodes. It’s going to continue. Many companies are looking it. They are deciding what they can’t or don’t want to integrate on 5nm. They are activity looking at how to partition systems.”
isn’t so easy. Plus, there are several packaging options on the table with various tradeoffs, such as 2.5D, 3D-ICs, chiplets and fan-out.
It’s safe to say that not all need advanced nodes. But Apple, HiSilicon, Intel, Samsung and Qualcomm require advanced technologies, and for good reason.
Consumers want the latest and greatest systems with more performance. The big question is whether the next technologies will provide any real benefits at the right cost.
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