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JEDEC is close to publish DDR5 memory standard


Tuesday, April 14, 2020

The DDR5 memory spec is due to be published, but details have remained scarce. When JEDEC, the organization responsible for developing memory standards, gets around to it is anyone's guess. Fortunately, South Korea's SK Hynix spilled the beans recently, providing some solid information.

DDR4, or Dynamic Data Rate version 4, came out in 2014. It started out at 1600 Mhz speeds and eventually reached 3200 Mhz at the very high end, with most DRAM in the low 2000 MHz range. At the time, that was enough. Intel's best Xeon processors had eight cores, and AMD was largely irrelevant.

Fast forward to 2020. AMD is thoroughly revitalized and shipping processors with 64 cores, while Intel is shipping 28-core chips and promising a 48-core chip. Ampere is promoting an 80-core Arm server processor, while Marvell has a 96-core Arm processor called ThunderX3.

Suddenly, 3200 Mhz memory isn't enough. And with data sets for AI and machine learning grower ever larger, memory was becoming a real bottleneck. DDR5 will address that. DDR5 will start at 3200 MHz and scale all the way up to 8400 MHz as time goes on.

Hynix plans for all of its DDR5 memory to run at least at 4800 MHz, and speeds below 4800 MHz will simply serve to conserve power. This means DDR5 memory will have 50% greater bandwidth than DDR4 at launch and only get faster. And the power draw is going down slightly, from 1.2 volts in DDR4 to 1.1 volts in DDR5.

Aside from the typical speeds and feeds improvements, DDR5 also increases its performance by something called "Same Bank Refresh." In DDR4, all the memory banks have to refresh simultaneously, even if only one of the 16 memory banks on the DIMM needs to be refreshed, leaving the CPU waiting if it needs the contents of another bank.

With DDR5, the number of banks is doubled to 32, but the Same Bank Refresh function means memory bank refreshes independently, while other banks remain accessible to the system. It's one more tool to squeeze out more performance and keep the cores fed rather than waiting.

"What's important about DDR5 is the high level of integration it provides," says Jim Handy, principal analyst with Objective Analysis, an analyst firm specializing in the memory market. "The people who defined this spec took advantage of the fact that Moore's Law not only reduces DRAM's price per bit, but it also makes it cheaper to add increasing amounts of powerful logic to the chip. They have artfully used this to improve the CPU-DRAM bandwidth, to move the Memory Wall a little farther out."

The Same Bank Refresh is a good example, Handy says. "For DRAM's entire history a chip couldn't provide data while it was being refreshed. Now Same Bank Refresh allows data to be accessed in banks that aren't undergoing refresh. This does a lot to improve data communication."

So when will this start to show up? Last year an Intel roadmap was leaked to the hobbyist press that showed Intel was planning to move to DDR5 and PCI Express 5 (completely skipping PCIe v4) in 2021. Micron has begun sampling DDR5, Hynix said it plans to begin volume production at the end of this year, and Samsung plans to start DDR5 production next year.

That means we can expect volume production to ramp in 2021, and mass market probably in 2022. And I expect servers will be first, as few desktops users will benefit from the changes in DDR5. Gamers and overclockers might be drooling at these specs, but the priority will likely be big iron, which has rapidly run up against the limitations of DDR4.

By: DocMemory
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