Friday, June 12, 2020
JEDEC has defined and developed three DDR standards – standard DDR, mobile DDR, and graphic DDR – to help designers meet their memory requirements. DDR5 will support a higher data rate (up to 6400 Mb/s) at a lower I/O Voltage (1.1V) and a higher density (based on 16Gb DRAM dies) than DDR4. DDR5 DRAMs and dual-inline memory modules (DIMMs) are expected to hit the market in 2020. This article outlines several key features of DDR5 DRAMs that designers can deploy in their system-on-chips (SoCs) for servers, cloud computing, networking, laptop, desktop, and consumer applications.
Standard DDR DRAMs, providing high-density and high-performance, are available in various types and form factors and support data widths of 4 (x4), or 8 (x8), or 16 (x16) bits. Applications can use these memories either as discrete DRAMs or DIMMs. DIMMs are printed circuit board (PCB) modules with several DRAM chips supporting either a 64-bit data width or a 72-bit data width. 72-bit DIMMs are called error-correcting code (ECC) DIMMs since they support 8 bits of ECC in addition to the 64 bits of data.
Servers, cloud, and data center applications typically use x72 ECC DIMMs based on x4 DRAMs, allowing higher density DIMMs and supporting higher RAS (Reliability, Availability, Serviceability) features to minimize the downtime of such applications during memory-related failures. DIMMs based on other x8 and x16 DRAMs are less expensive and are commonly implemented in desktops and notebooks. In addition, applications can use these memories as discrete DRAMs. Hence, flexibility on channel-width is the biggest advantage of standard DDR over the other DDR categories.
Key Features of DDR5
A burst length of 16 beats, better refresh/pre-charge schemes allowing higher performance, a dual-channel DIMM architecture targeted at better channel utilization, integrated voltage regulators on DDR5 DIMMs, increased bank-group for a higher performance, and Command/Address on-die termination (ODT) are just a few of the many new DDR5 high-performance features. Table 1 compares the high-level features between DDR5 and DDR4 DRAM/DIMMs.
Besides performance, DDR5 also introduces several RAS features to ensure channel robustness at increased speeds. Some of these features resulting in higher DDR5 channel robustness include duty cycle adjuster (DCA), on-die ECC, DRAM receive I/O equalization, Cyclic Redundancy Check (CRC) for both RD and WR data, and internal DQS delay monitoring. The following section describes each of these features.
Duty Cycle Adjuster (DCA) for Compensating Duty Cycle Distortion
The duty cycle adjuster allows the host to compensate for duty cycle distortion on all DQS (data strobe)/DQ (data) pins by adjusting the duty cycle inside the DRAM. Hence, the DCA feature enhances the robustness of the read data.
On-die ECC for Enhanced RAS
For every 128 bits of data, DDR5 DRAMs will have 8 bits of storage for ECC. Hence, on-die ECC becomes a powerful RAS feature to protect the memory array against single-bit errors.
DRAM Receive DQ Equalization for Better Margins
Like LPDDR5 DRAMs, DDR5 DRAMs will also support equalization for the WR data. This feature opens the WR DQ eye at the DRAM end, protecting the channel from inter-symbol interference (ISI), improving margins, and enabling higher data rates.
Cyclic Redundancy Check (CRC) for both RD/WR data
While DDR4 supports CRC only for the WR data, DDR5 extends CRC to the RD data, allowing additional protection against errors occurring on the channel.
Internal DQS Delay Monitoring
The internal DQS delay monitoring mechanism allows the host to adjust DRAM delays to compensate for voltage and temperature variations. At DDR5 speeds, the host can use this feature to retrain the channel periodically, compensating for VT variations on delays in the DRAM.
Designers have many options when it comes to choosing the best off-chip memory technology for their design to meet the requirements of their target application. DDR has become the de facto technology, available in many generations, doubling its data rate with every generation from DDR at 400 Mbps to DDR5 at 6400 Mbps. DDR5 is expected to offer higher density including a dual-channel DIMM topology for higher channel efficiency and performance with increasing core counts. These advantages are most significant for SoCs targeting server, cloud computing, networking, laptop, desktop, and consumer applications.
No matter what DDR DRAM technology designers choose, they must also deploy compliant interface IP solutions in their SoC that allow the required connectivity to and from the DRAM. Synopsys provides a silicon-proven DDR memory interface IP portfolio that enables DDR5/4/3/2, LPDDR5/4/4X/3/2, and HBM/HBM2E DRAMs or DIMMs. The DesignWare DDR IP complete solution includes controllers, an integrated hard macro PHY in mainstream and advanced FinFET processes, and verification IP. In addition to enabling designers to meet unique, high-performance application requirements with our hardening expertise, Synopsys provides signal integrity/power integrity analysis, verification models, prototyping, and emulation support.
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