Cadence Design Systems Inc. is expanding its collaboration with Taiwan Semiconductor Manufacturing Co. Ltd (TSMC) to accelerate mobile, AI and hyperscale computing application design using the integrated Cadence digital flow and custom/analog tool suite on TSMC’s N3 and N4 process technologies. Joint Cadence and TSMC customers have already successfully used the digital and custom/analog tools to complete test chip tapeouts.

As part of the collaboration, the Cadence digital and custom/analog tools have been optimized and certified for TSMC’s N3 and N4 process technologies, supporting the latest Design Rule Manual (DRM) certification and SPICE correlation. The corresponding N3 and N4 process design kit (PDKs) are available now. The digital and custom tool suites support the Cadence Intelligent System Design strategy, enabling customers to achieve SoC design excellence.

N3 and N4 Digital Flow Certification

The Cadence digital flow has been finely tuned and certified for use on TSMC’s N3 and N4 process technologies, providing customers with optimal power, performance and area (PPA) and shortening time to market. The complete RTL-to-GDS flow includes the Innovus Implementation System, Liberate Characterization Solution, Quantus Extraction Solution, Tempus Timing Signoff Solution and ECO Option and Voltus IC Power Integrity Solution for electromigration and IR drop analysis. In addition, the Genus Synthesis Solution and its predictive iSpatial technology is enabled for these process technologies.

Some of the tool suite capabilities that enable customers to successfully design mobile, AI and hyperscale computing applications include: Advanced rule support from synthesis to signoff engineering change orders (ECOs); large libraries containing many multi-height, voltage threshold (VT) and drive strength cells; and low-voltage call characterization and timing analysis accuracy.

N3 and N4 Custom/Analog Tool Suite Certification

TSMC and Cadence have continued to collaborate to optimize custom design methodologies and address complex simulation requirements within Cadence’s Virtuoso and Spectre environments to improve overall designer efficiency. In support of the collaboration, Cadence delivered an enhanced custom design reference flow (CDRF), and the Virtuoso Design Platform and the Spectre Simulation Platform have achieved TSMC N3 and N4 certifications. Also, the Virtuoso Platform’s tight integration with the Innovus Implementation System provides a single, unified environment for TSMC’s advanced-node mixed-signal customers.

Custom design flow enhancements for TSMC’s N3 and N4 process technologies include an enhanced N3 schematic design migration flow and advanced coloring feature support for both N3 and N4 processes.

“By broadening our collaboration with Cadence, we’re providing our customers with certified flows and PDKs they need to quickly adopt the advanced TSMC N3 and N4 process technologies,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “We’ve seen our customers successfully complete test chip designs and tapeouts on our latest advanced processes and are looking forward to our continued partnership with Cadence to enable next-generation designs for mobile, automotive, AI, and hyperscale applications.”

“Our latest collaboration with TSMC has enabled mutual customers to leverage the combined benefits of TSMC’s N3 and N4 process technologies using our digital flow and custom flow,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “Our customers have achieved positive results already, and we’re looking forward to enabling more incredible innovations, which stem from our dedication to SoC design excellence.”

By: DocMemory
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