Like all iterations of DRAM, DDR5 will need an ecosystem of supporting technologies for it to become dominant, even as advanced workloads drive memory bandwidth requirements.

Rambus Incorporated is already laying the groundwork for DDR5 implementations more than a year away. The company recently announced it is sampling its 5600 MT/s 2nd-generation DDR5 registering clock drivers (RCD) to the major DDR5 memory module (RDIMM) suppliers. John Eble, vice president of product marketing for memory interface chips, said it will be several years before systems will be hitting the market. However, supporting technologies such as its RCD need to be evaluated and qualified by customers now so the ecosystem is ready to provide the bandwidth and capacity that will be required in next-generation data centers.

A DDR5 RCD along with data buffers (DB) are used in DDR5 Registered DIMMs (RDIMMs) and DDR5 Load Reduced DIMMs (LRDIMMs) to deliver higher bandwidth, performance, and capacity when compared to unbuffered DIMMs. RDIMMS, and LRDIMMs to reduce load on the CPU and improve the signal integrity of the command/address bus. The role of the RCD is as a key control plane chip which distributes Command/Address signals and clock to the DRAM devices on the DIMM. Rambus’ RCD can support DDR5 LRDIMMs when paired with 10n DB chips per module and reduces the effective load on the data bus to enable higher-capacity DRAMs on the module without reducing latency.

A distinguishing feature of DDR5 memory is that more intelligence is built into the DIMMs, which allows for as much as double the data rate and four times the capacity of DDR4 DIMMs. Eble said the performance of Rambus’ latest DDR5 RCD delivers a 17% increase in data rate over its first-generation 4800 MT/s DDR5 RCD with 5600 MT/s performance at lower latency and power, while also optimizing timing parameters for improved RDIMM margins. The company is already shipping its first-generation RCD in reasonable quantities as customers look to ready their product launches for next year, he said.

Servers are requiring larger capacity, higher bandwidth, and faster boot time from memory, while also expecting the same access granularity and the same or better same or better reliability, availability, and serviceability features as previous iterations of DRAM. Eble said newer DIMMs must also remain within a cooling power envelope of ~15W per DIMM. Energy costs are critical to the total cost of ownership (TCO) of data centers, particularly those of hyperscalers, both in terms of powering the system itself and the power needed to cool it. “There is an advantage to going to these denser cores. You’re doing more within a single box.”

That scalability is critical, said Eble, especially as the demands of servers has been what’s been driving the move to DDR5 standard. Ultimately, it’s about enabling the DDR5 ecosystem so that customers can continue at a pace they want to as they roll out DDR5 systems.

DDR5 has both similarities and differences with its predecessor. In addition to having better performance, capacity, and power consumption, a DDR5 DIMM features increased parallelism and an improved signaling rate compared to a DDR4 DIMM. Eble said this allows for more capacity and bandwidth by putting more DRAM together in parallel. DDR5 has a 40-bit data channel (32 data + 8 ECC) with two channels per DIMM that enables higher memory efficiency and lower latency. The downside of having multiple slots per channel is that the data lines and the command address lines can get heavily loaded. “That’s where the memory interface chips come in.” He said having two channels instead of one isn’t necessary to improve bandwidth, there are benefits to the increased parallelism. “It does give the CPU more parallel resources to more things in flight.” Eble said the huge growth of data and the processing of it through artificial intelligence and machine learning is a big driver of DDR5 adoption, hence the focus on the needs of next generation data centers. However, content creation and consumption will also drive the adoption of the latest iteration of DRAM, and that’s what Micron’s recently announced Crucial DDR5 desktop PC memory products are looking to address. Desktop users are expecting more efficient multitasking and better performance for emerging PC applications?such as 4K and 8K content creation, interactive entertainment, personal and business productivity, and virtual reality experiences, all of which benefit from the combination of higher bandwidth, lower power, and higher density of DDR5. The new crucial DDR5 memory is compatible with 12Gen Intel Core processors that support DDR5 and is available in 8GB, 16GB and 32GB densities, and the company said it will deliver up to 50% faster data transfer speeds compared to previous generation DDR4 memory.

The DDR5 SDRAM standard was initially launched in July 2020 by the JEDEC Solid State Technology Association, which recently announced an update with publication of the JESD79-5A DDR5 SDRAM standard. It includes features designed to enhance reliability and performance in a wide range of applications involving client systems and high-performance servers.

New features in the update are aimed at improving system reliability, including bounded fault error-correction support, Soft Post-Package Repair (sPPR) undo and lock, Memory Built-In Self-Test Post Package Repair (MBIST and mPPR), Adaptive RFM, and an MR4 extension. The JESD79-5A update also expands the timing definition and transfer speed of DDR5 up to 6400 MT/s for DRAM core timings and 5600 MT/s for IO AC timings to enable the industry to build an ecosystem up to 5600 MT/s.

By: DocMemory
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