Power management integrated circuits (PMICs) primarily provide required voltage levels in electronics applications. Many PMICs, as well as other mixed signal devices use 5V transistors as switches. Switch performance is strictly related to two key factors: low on-resistance, reducing power losses; and good isolation, or high-breakdown voltage. Hence, the standard metric for switch performance is on-resistance at a given breakdown voltage.

Atomera Inc., an IC materials engineering specialist based in Los Gatos, California, has unveiled proprietary technology designed to improve the performance of 5V analog transistors by reducing channel on-resistance. The patented Mears Silicon Technology (MST) combines carrier mobility improvements, thereby reducing specific on-resistance, with dopant profile engineering that provides better control of short channel effects. Dubbed MST Smart Profile, the 5V NMOS switch achieves as much as 25-percent reduction in specific on-resistance without compromising breakdown voltage or other relevant device characteristics.

The goal is “to provide the smallest footprint and cost for these devices in the market,” said Atomera CTO and Founder Robert Mears. “It is targeting the fast-growing PMIC market and other analog power IC markets as well.”

MST, a quantum engineered thin-film developed during more than 15 years of research and development, is an epitaxially grown film consisting of a non-semiconductor material such as oxygen inserted into silicon or other semiconductor materials. Oxygen is epitaxially deposited within the films in order to modify or enhance basic semiconductor properties and device characteristics, including diffusion blocking, variability, mobility, gate leakage and reliability.

According to Atomera, the technology is supported by major epitaxy tool suppliers since epitaxial growth enables MST. Atomera engineers have gained much experience developing MST films with special qualities. The proprietary epitaxial techniques enable atomistic epitaxial growth and deposition. MST film quality is evaluated during volume manufacturing using tools such as spectroscopic ellipsometry metrology.

Said Mears: “We can think of a transistor as a set of three optimization points: speed, area and power density. By applying MST to a transistor with the same device footprint, we can actually get quite a bit more drive current out of the device.”

MST benefits include better power performance area, higher speed, lower cost since transistor size can be shrunk until drive currents match and reduced power–VDD can be reduced until drive currents match.

A combination of speed, size and power density can be mixed and matched in order to best fit the requirements of specific applications

MST can be used to reduce power consumption by reducing leakage while also boosting performance. Dealing with increased gate leakage at lower process geometries is among the most difficult tasks for chip designers. During third-party tests, gate leakage reductions of more than 60 percent were demonstrated by preventing unwanted transistor current flow in the vertical direction. Another option for reducing power consumption is trading performance advantages for lower voltages.

Atomera has developed two processes for integrating MST into process flows. In the first, blanket wafers are created via oxygen-rich, layered films. Wafers are then processed as part of the chip manufacturing process. Integration is straightforward but lacks flexibility since the technology must be applied to all devices on the wafer, then each device must be re-optimized. MST1 is suited for low thermal Dt processes, such as FinFET and RF SOI.

For analog and power devices, the MST2 process is more selective and therefore more flexible. Hence, process technology is applied only for selected devices using an additional hard mask.

While targeting the vibrant PMIC market, Atomera’s technology could also be applied to analog and power IC applications. Thanks to a mobility enhancement and the precision doping, MST SP promises a smaller area for power devices. “We can actually take an existing process, insert the MST technology, optimize the MST SP device and end up with a smaller and higher performance 5V power device,” said Mears.

Although it has been optimized for 5V transistors, the technology is expandable to other voltages. MST SP provides higher Idlin and reduced Lg (0.25µm) for given reliability, enabling a lower Rsp which, in turn, enables power devices up to 20 percent smaller.

MST technology can be simulated using MSTcad, Atomera’s tool for modeling physical properties as well as the full MST process during device manufacturing. Results obtained with MSTcad have been confirmed by Atomera on silicon, enabling accurate MST integration into semiconductor devices. MSTcad is currently available from Atomera as an add-on to the Sentaurus Process and Device simulation packages used for physical and electrical characterization.

“The reason why we have been able to achieve these enhancements is not just because of the MST technology, but also [through] our understanding of how we can apply the technology to the baseline. To do that, we have run a lot of simulations with MSTcad,” said Mears.

The tool, consisting of a set of Alagator scripts incorporating MST physics, is calibrated against silicon provided by TSI Semiconductors. It is used internally to optimize TSI foundry silicon, and by individual licensees and customers to boost process efficiency.

By: DocMemory
Copyright © 2023 CST, Inc. All Rights Reserved