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MIPS to focus on RISC-V based multiprocessor IP core products

Friday, May 13, 2022

MIPS has re-emerged with fanfare this week, announcing a new focus on delivering RISC-V based products for high performance processing, and announcing the first of its RISC-V based multiprocessor IP core products, the eVocore P8700 and I8500, based on the open instruction set architecture (ISA).

The company said its new eVocore family of IP cores are highly scalable and configurable, enabling customers to blend coherent clusters of multi-threaded, multi-core CPUs in unique combinations to meet their exact power and performance requirements. These features help target automotive, communications and networking, plus high-performance computing (HPC) and datacenters. The cores are designed to provide a flexible foundation for heterogeneous compute, supporting combinations of eVocore processors as well as other accelerators, with a coherence manager that maintains L2 cache and system-level coherency between all cores, main memory, and I/O devices.

Because the RISC-V ISA enables the addition of custom features in the form of user defined instructions (UDIs), MIPS said it can uniquely deliver proven and powerful features which are required in many high-end applications, while also being fully compatible with off-the-shelf RISC-V development tools and software libraries.

Both the new eVocore P8700 and I8500 IP cores provide support for privileged hardware virtualization, user defined custom extensions, multi-threading, hybrid debug, and functional safety. These features and the high level of scalability of the cores make them suited for compute-intensive tasks across a broad range of markets and applications such as automotive (ADAS, AV, IVI), 5G and wireless networking, data center and storage, and high-performance embedded applications.

The company announced details at ChipEx 2022 in Israel this week. In an interview with embedded.com, Itai Yarom, vice president for sales & marketing at MIPS, explained the new direction for MIPS, saying it was an evolution. “We are taking the MIPS microarchitecture proven in billions of products and building on this as we pivot our focus around the RISC-V ISA. The main reason we chose RISC-V is because the adoption cost of software is lower, and this helps accelerate product development [for customers].”

His CEO, Desi Banatao, added, “With this transition to RISC-V, MIPS is targeting the high-performance segment of the processor market. By leveraging our differentiation in real-time features, hardware virtualization, functional safety and security technologies, we can offer compelling products for automotive, edge compute, networking and switching, and large-scale computing systems.”

Rich Wawrzyniak, principal ASIC and SoC analyst, Semico Research, commented, “We will see continued adoption of RISC-V in areas such as automotive as companies see the possibilities for differentiation that an open software development environment can provide, With MIPS’ long history providing RISC architectures and cores and its strong footprint in automotive, networking and other high-performance applications, the company’s move to RISC-V makes sense for the next stage of its growth.”

In talking to MIPS, the company made it clear that it is targeting high performance. Yarom said that they already have design wins in automotive for the P8700, its’ flagship processor of the family so far. He said the single thread and multi-thread options enables it to deliver at least twice the performance of other RISC-V based processors. He said that enabling high performance on RISC-V is not trivial, since it requires building the system in an efficient way to get the memory and bandwidth. “With our new eVocore we can help the RISC-V community to add greater performance capability.”

Clearly, RISC-V International was pleased with MIPS’ new direction. CEO Calista Redmond said, “We are delighted that MIPS, one of the pioneers of RISC CPU architectures, is turning its attention to RISC-V. MIPS has long been used in high-end computing, an area where RISC-V is beginning to gain significant traction. MIPS is bringing to the RISC-V community a heritage of CPU innovation and new RISC-V compatible CPUs designed for flexibility and scalability.”

The eVocore P8700 is a multiprocessing system geared towards delivering superscalar performance, combining a deep pipeline with multi-issue out-of-order (OOO) execution and multi-threading to deliver “outstanding” computational throughput. It has single-threaded performance greater than what is currently available in other RISC-V CPU IP offerings, and it can scale up to 64 clusters, 512 cores and 1,024 harts/threads. The eVocore P8700 will be available in Q4 2022.

Meanwhile, the eVocore I8500 is an in-order multiprocessing system with best-in-class power efficiency for use in SoC applications. Each I8500 core combines multi-threading and an efficient triple-issue pipeline to deliver outstanding computational throughput.

By: DocMemory
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