Researchers at the Bengaluru-based Indian Institute of Science (IISc) have developed a design framework to build next-generation analog computing chipsets that promise to be faster and require less power than the digital chips found in most electronic devices.

Using their new framework, the team has built a prototype of an analog chipset called ARYABHAT-1 (short for Analog Reconfigurable technologY And Bias-scalable Hardware for AI Tasks). The new chipset is expected to be especially helpful for artificial intelligence (AI)-based applications like object or speech recognition such as Alexa or Siri or those that require massive parallel computing operations at high speeds.

Presently, most electronic devices, particularly those that involve computing, use digital chips because the design process is simple and scalable. However, researchers have also been working on analog chips as they may allow for orders of magnitude improvement in power and size. In applications that don’t require precise calculations also, analog computing is expected to have the potential to outperform digital computing as the former is more energy-efficient.

But, there are several technical hurdles to overcome while designing analog chips. For instance, testing and the co-design of analog processors is complex, and they don’t scale up quickly. They need to be individually customised when transitioning to the next generation technology or a new application. Another challenge is that trading off precision and speed with power and area is not easy.

he team has sought to overcome these challenges. Their chipset can be reconfigured and programmed so that the same analog modules can be ported across different generations of process design and across different applications.

“You can synthesise the same kind of chip at either 180nm or at 7nm, just like digital design,” says Chetan Singh Thakur, Assistant Professor at the Department of Electronic Systems Engineering (DESE), IISc.

According to the researchers, different machine learning architectures can be programmed on the framework, and operate robustly across a wide range of temperatures. In addition, the architecture is “bias-scalable” – its performance remains the same when the operating conditions like voltage or current are modified. This means that the same chipset can be configured for either ultra-energy-efficient Internet of Things (IoT) applications or high-speed tasks like object detection.

The design framework was developed as part of IISc student Pratik Kumar’s Ph.D. work, and in collaboration with Shantanu Chakrabartty, Professor at the McKelvey School of Engineering, Washington University in St Louis (WashU), USA, who also serves as WashU’s McDonnell Academy ambassador to IISc.

The researchers have outlined their findings in two pre-print studies currently under peer review. They have filed patents and are planning to work with industry partners to commercialize the technology.

By: DocMemory
Copyright © 2023 CST, Inc. All Rights Reserved