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Intel put emphasis on RISC-V cores

Monday, September 19, 2022

Intel has taken a significant new step in supporting wider adoption of RISC-V cores by launching a unified integrated development environment (IDE) called Intel Pathfinder, along with partner ecosystem of intellectual property (IP) providers, operating systems, tool chains and software to support new product development.

The premise behind the new Intel Pathfinder platform is that system-on-chip (SoC) architects and system software developers can create their own products using a variety of RISC-V cores and intellectual property (IP) from the partner ecosystem, instantiate on FPGA and simulator platforms, and then run industry leading operating systems and tool chains within a unified IDE. This makes it simpler and quicker to assemble and test different IP combinations in a single environment, and still be supported with robust software and industry standard toolchains that allow for seamless scaling for a broad spectrum of customers.

In an interview with embedded.com, Vijay Krishnan, general manager of RISC-V Ventures at Intel, said, “Developers finally have a product that users can download and use. Intel Pathfinder for RISC-V represents our ongoing commitment to accelerate the adoption of RISC-V and catalyze the ecosystem around an open-source and standards-based vision. The starter edition will help proliferate usage of RISC-V, where the user can use it as a software product, with no hardware required. It is based on a generic RISC-V core running on a software emulator. And then, the power user can get a starter FPGA board for $449 and instantiate specific RISC-V cores.”

Intel Pathfinder is initially available in two versions, the ‘Starter Edition’ and the ‘Professional Edition’. The Starter Edition which Krishnan refers to above is primarily intended for the hobbyist, academia and research community and is available as a free download. The Professional Edition comes with broad ecosystem support, and targets organizations involved in commercial RISC-V based silicon and software. This edition will be made available based on customer needs and underlying product capabilities.

On the Professional Edition, Krishnan said, “We’ve been working on this for over a year, and now, all the ecosystem partner companies have agreed to work with us, bringing their cores over to our systems. Commercial companies can hence use Pathfinder for RISC-V free, with ecosystem companies managing the distribution and licensing costs.”

Processor cores and IP

Among the cores offered within the Intel Pathfinder platform are MIPS’ eVocore P8700 and I8500 multiprocessor IP cores, the first MIPS products based on the RISC-V open ISA standard. The Intel Pathfinder FPGA development platform incorporates these MIPS cores within a unified IDE, supporting leading operating systems and industry-standard toolchains. MIPS said this will open up new opportunities for developers to quickly build prototypes for segments like automotive which have additional functional safety (FuSa) requirements. Desi Banatao, MIPS’ CEO, said, “This is a unique and important capability for startups because it can enable them to explore their solution and accelerate the rate at which they can find a product market fit.”

Andes Technology announced two CPU processor cores are to be available in the Intel Stratix 10 GX FPGA development kit as part of Intel Pathfinder. Its 64-bit superscalar multicore AX45MP processor IP and 64-bit vector processor core NX27V with up to 512-bit vector length, both pre-integrated with AXI-based AE350 platform, are to be available in the Intel development kit. This enables SoC design teams to boot Linux OS or upload their critical compute kernels to the FPGA board to quickly explore the benefits of AX45MP and NX27V before first silicon.

Meanwhile, Codasip said its 32-bit L31 core will be available through the Professional Edition of the Intel Pathfinder for RISC-V program. In the cooperation, Intel FPGA boards and Intel software stack can be combined with a Codasip bitmap file for the L31 RISC-V core. This benefits developers in applications such as internet of things (IoT) and edge AI. By joining the program, the company said its embedded RISC-V technology will become more accessible for prototyping, production design or research purposes using Intel FPGAs. Particularly in the early stages of the SoC development cycle, it is beneficial to undertake architectural exploration and to explore different configurations and combinations of IP. The Intel Pathfinder provides a common environment for accessing RISC-V and peripheral IP through its FPGA boards.

Solving the perceived ecosystem problem

The RISC-V community has certainly been gaining market traction, but for those outside it there’s still a perceived element of risk in adopting the open-source model. The main argument we often hear is that the ecosystem is not as robust for RISC-V as incumbent architectures. Intel has addressed this fear directly by pulling together some of the key players in the community and providing a platform for users to design with confidence that there is support. Krishnan said, “With our FPGA boards, we are trying to make the experience real. Before you make the leap to RISC-V, you can use the FPGA board to test, evaluate and implement with confidence.”

Terasic developer kit for Intel Pathfinder for RISC-V

Krishnan heads up RISC-V Ventures, which was formed over a year ago under the Incubation and Disruptive Innovation (IDI) Group at Intel led by Sundari Mitra, who is the chief incubation officer at Intel. The charter for IDI is to identify and new grow business opportunities. Mitra said, “The launch of the Intel Pathfinder for RISC-V illustrates our continued commitment to bring these opportunities to life.”

More specifically, Krishnan said that Intel likes the open and modular nature of RISC-V. “We definitely see RISC-V has broad market adoption, put the pace of its evolution has not seen it go mainstream yet. That’s why we want to help foster this ecosystem since we are open to new architectures and want to help reduce design friction.”

By: DocMemory
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