Tuesday, November 1, 2022
The fabrication process of any semiconductor can be divided into five main phases: crystal growth, slicing and grinding, polishing, epitaxy (epi), and device manufacturing. The third step, which we have generally called “polishing,” is the last phase of substrate production. This step is particularly important to atomically smooth the substrate’s surface, obtaining a high level of planarity, essential for the subsequent processing of the wafer.
Although Chemical Mechanical Polishing (CMP) has been the most used technique for substrate polishing for some time, a newly introduced technology, Plasma Polish Dry Etch (PPDE), is emerging as a valid alternative proposed by Oxford Instruments Plasma Technology, a business unit of Oxford Instruments Plc., that can overcome some of the limitations offered by CMP.
At the recent International Conference on Silicon Carbide and Related Materials (ICSCRM), held Sept. 11–16, 2022, in Davos, Switzerland, Oxford Instruments launched its new Plasma Polish process for SiC substrates. Announced as a direct replacement for conventional CMP technology, Plasma Polish aims to neatly fit in that demand gap where CMP currently is.
Plasma Polish Dry Etch
This article is focused on the PPDE technology developed by Oxford Instruments, a company founded in the late 1950s as a spinout of the University of Oxford. Today, the company provides high-technology products and services to many of the world’s leading companies and scientific research communities.
“I would say that nearly 50% of our business at Plasma Technology is focused on corporate R&D and universities,” said Brian Dlugosch, VP of Strategic Production Markets at Oxford Instruments Plasma Technology. “However, the remaining 50% of our business is based around servicing production customers, but it’s trending significantly toward production as our compound solutions gain traction in high-growth markets reliant on advanced materials.”
According to Dlugosch, silicon carbide is one of the products that Oxford Instruments is looking to get into production customers, due to the high demand from the market for this semiconductor and the consequent high-volume manufacturing process it requires.
According to market analyses, the forecast for the 6-inch wafer supply in the automotive industry is growing with a clear demand gap, which is a real challenge for the entire electronics industry. The solution is currently at 150mm, but the hardware is 200-mm production-compatible. The company’s patented approach provides smooth and damage-free SiC substrate surface and subsurface. That achievement is essential for enabling low-defect density epitaxial growth.
“CMP has limitations that could slow the adoption of SiC in devices used in e-mobility and sustainable energy. Plasma Polish can overcome these limitations and scale to meet the needs of these high-growth markets,” said Dlugosch.
The plasma-polishing technique is scalable, providing the same outcomes to SiC substrates regardless of wafer size. This enables the application of industry-standard wafer handling, monitoring, and control techniques that decrease contact time while boosting yield and efficiency.
Besides lack of scaling, CMP suffers from some limitations involving large environmental costs and, ultimately, high opex costs including slurry byproducts, which are expensive to buy, are costly to dispose of, and require extreme water usage. Almost 40% of the water usage in a semiconductor fabrication plant is related to CMP. Moreover, the physical pressure that CMP applies to the wafer means that breakage issues might occur.
“The first benefit of our Plasma Polish process is the reduction in cost,” said Dlugosch. “Compared to CMP, Plasma Polish cost per wafer is lower, there is less chemical and consumable usage, and process stability is greatly improved.”
Chemical mechanical processes put stress on the substrate, which increases wafer loss and fracture. As the particles scrape against the SiC, scratches are left on the surface. Plasma Polish is a contactless method for selectively removing damaged SiC from the surface while maintaining good surface quality.
Other benefits of PPDE are lower cost per wafer, less chemical and consumables usage, and better process stability and MTBC.
One critical aspect to understand about what is happening at the wafer surface and subsurface is that smoother does not necessarily equal better. CMP planarizes the SiC surface very well, and leaves a flat topography, but it is not always efficient to target subsurface damage. Conversely, Plasma Polish selectively targets defective and damaged material that is weakly bonded and etches more readily. This last aspect is highlighted in the diagrams in Figure 1. What remains is not necessarily smoother, but is a higher quality crystal.
Oxford Instruments has validated its Plasma Polish process in 2 steps. The first one consisted of validating the properties of the epi-layer by KOH etch, Candela and epi-surface roughness. The second step involved validating the Plasma Polished substrates by making devices in collaboration with its partner, Clas-SiC Wafer Fab. Operating in its foundry in Scotland, Clas-SiC was provided with both CMP- and PPDE-prepared wafers and assessed the quality of the wafers, running them through the same device line for diodes and MOSFETs. Whole wafers of 1,200-V SiC MOSFET devices were qualified, providing parametric results and yield comparable, or maybe even slightly better as far as yield is concerned, to those of CMP-prepared wafers.
Ultimately, the assessment performed by Clas-SiC has shown that epi grown on PPDE substrates has the same properties of the one grown on CMP substrates, and MOSFET devices showed comparable performance. Oxford Instruments has shared at the recent ICSCRM the full-wafer performance data obtained by Clas-SiC.
“We believe our solution offers significant advantages to CMP, as an environmentally friendly solution with lower cost and potentially higher yields,” said Dlugosch.
SiC substrates are currently in short supply due to high demand, and the wide-bandgap semiconductors that are produced on the substrates are also in demand. New solutions are required, as this manufacturing gap is expected to rise exponentially as the high-growth electric-vehicle and sustainable energy markets use more and more of these compound semiconductors in their applications. Plasma polishing, according to Oxford Instruments, is a plug-and-play substitute for CMP that immediately lowers the cost per wafer with reduced operating expenditure but is also a key enabling technology to accelerate the transition to 200 mm.
“We’ve validated and launched a cleaner, greener, lower cost alternative to CMP, which has the potential to overcome the technological limitations of CMP and accelerate SiC adoption into some truly exciting applications,” said Dlugosch.
For every car on the road to be electric, longer-driving–range EVs should not only be the norm, but batteries should be more affordable and faster to charge. As silicon is reaching its theoretical limits, the industry is shifting to SiC for power electronics because of its wider bandgap, higher breakdown electric field, and higher thermal conductivity. SiC-based MOSFETs indeed achieve lower losses, higher switching frequencies, and higher power densities than silicon components.
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