Home
News
Products
Corporate
Contact
 
Saturday, May 18, 2024

News
Industry News
Publications
CST News
Help/Support
Software
Tester FAQs
Industry News

TSMC runs into too supply probem on 3nm note process


Friday, May 19, 2023

Taiwan Semiconductor Manufacturing Co. (TSMC) is straining to meet demand from top customer Apple for 3-nm chips. The company’s tool and yield struggles have impeded the ramp to volume production with world-leading technology, according to analysts surveyed by EE Times.

TSMC and Samsung, its next largest rival in the foundry business, are racing to be first in 3-nm production for customers like Apple and Nvidia in high-performance computing (HPC) and smartphones. TSMC became the latest to claim 3-nm leadership in its quarterly results announcement last month.

“Our 3-nm technology is the first in the semiconductor industry to high-volume production with good yield,” TSMC CEO C.C. Wei said in a recent conference call with analysts. “As our customers’ demand for N3 [TSMC terminology for 3 nm] exceeds our ability to supply, we expect N3 to be fully utilized in 2023, supported by both HPC and smartphone applications. Sizable N3 revenue contribution is expected to start in the third quarter, and N3 will contribute a mid-single–digit percentage of our total wafer revenue in 2023.”

TSMC, Samsung and Intel are aiming for technology leadership to serve customers that include Apple, Nvidia and others designing data center CPUs. The eventual leader will garner the lion’s share of profits in the foundry business, which for decades has outpaced the growth of the overall semiconductor industry. For now, TSMC keeps the top spot, according to Mehdi Hosseini, senior equity research analyst with Susquehanna International Group.

The trick for a foundry is making extremely expensive production tools from multiple suppliers perform together at peak efficiency.

“TSMC, in our view, remains the preferred foundry choice for leading-edge nodes as Samsung Foundry has yet to demonstrate a stable leading-edge process technology, all while IFS [Intel Foundry Services] is years away from offering a competitive solution,” Hosseini said in a report he provided to EE Times.

Leading-node customers

In the second half of 2023, TSMC will ramp Apple’s A17 and M3 processors at the N3 node, as well as ASIC-based server CPUs at N4 and N3, according to Hosseini said. TSMC will also fabricate Intel’s Meteor Lake graphic chiplets at N5, AMD’s Genoa and Nvidia’s Grace processors at N5 and N4, as well as Nvidia’s H100 GPU at N5, Hosseini said in the report.

Apple will pay TSMC for known good die rather than standard wafer prices, at least for the first three to four quarters of the N3 ramp as yields climb to around 70%, Brett Simpson, senior analyst at Arete Research, said in a report provided to EE Times.

“We think TSMC will move to normal wafer-based pricing on N3 with Apple during the first half of 2024, at around $16-17K average selling prices,” Simpson said. “At present, we believe N3 yields at TSMC for A17 and M3 processors are at around 55% [a healthy level at this stage in N3 development], and TSMC looks on schedule to boost yields by around 5+ points each quarter.”

For the iPhone A17 chip, TSMC will do 82 mask layers with a die size likely in the 100-110 mm square range, the Arete report said. That means a yield of around 620 chips per wafer with a wafer cycle time of four months, the report added. M3 is likely to be around 135-150 mm square die size and around 450 chips per wafer, according to Arete.

“The focus now for TSMC through this early ramp is to optimize yield and wafer cycle-times to drive efficiencies,” Simpson said.

TSMC has delayed the introduction and ramp of 3 nm due to a need to adopt multi-patterning with EUV lithography from tool supplier ASML, Hosseini said.

“While the high cost of EUV multi-patterning has made the cost/benefit of EUV unattractive, loosening the design rules to minimize the number of EUV multi-patterning layers has led to a much higher die size,” Hosseini said. The “real” 3-nm node will not scale until a higher-throughput EUV system, ASML’s NXE:3800E, is available during the second half of 2023, he added.

The NXE:3800E will help improve wafer throughput by about 30% over the current NXE:3600D by lowering the overall cost of EUV multi-patterning, according to Hosseini.

TSMC will accelerate adoption of the NXE:3800E in the first half of 2024 as the foundry scales N3E and other variations of the 3-nm node for more customers, Hosseini said in the report.

TSMC is getting help from customer Nvidia in lithography.

The “cuLitho” software and hardware is moving expensive operations to Nvidia GPUs, which will help TSMC deploy inverse lithography and deeper learning, according to C.C. Wei.

“We recently see TSMC partnered up with Nvidia, Synopsys and ASML on 2-nm production and beyond,” said Brad Lin, research analyst at Bank of America. “TSMC is currently the only foundry within that group.”

Keeping the lead

TSMC expects its next node, N2, will start production in 2025.

“At N2, we are observing a high level of customer interest and engagement,” Wei said. “Our 2-nm technology will be the most advanced semiconductor technology in the industry in both density and energy efficiency when it is introduced and will further extend our technology leadership well into the future.”

The current chip inventory correction that’s sweeping the industry has been at a higher level than TSMC expected three months ago and may extend into the third quarter this year, the company said. As a result, TSMC now expects that its 2023 revenue may fall for the first time in nearly a decade. The company that’s a bellwether for the electronics industry forecasts that its sales may drop by as much as a mid-single–digit percentage point.

“We think for other foundry players, sales could be down more than this in ’23, with a muted second-half recovery the norm,” Simpson said.

Despite the slump, TSMC is sticking with the same capital expenditure budget it had last year, somewhere in the range of $32 billion to $36 billion. With its equipment utilization down, TSMC is counting on a rebound in business during the third quarter.

Utilization is a key indicator of profitability.

“We expect the blended utilization rate to trough in the second quarter of 2023 at around 66%, with the N7 utilization rate dipping below 50%,” Hosseini said. “We expect utilization rates to show a rebound into the second half of 2023, driven by new product ramps.”

By: DocMemory
Copyright © 2023 CST, Inc. All Rights Reserved

CST Inc. Memory Tester DDR Tester
Copyright © 1994 - 2023 CST, Inc. All Rights Reserved