Marvell’s introduction of high-speed silicon interconnects made on the new 3-nm process at Taiwan Semiconductor Manufacturing Co. (TSMC) promises to stitch together chiplets that cut power consumption in data centers, Mark Kuemerle, VP of technology at Marvell, told EE Times

The die-to-die interconnects will enable data transfer speeds up to 240 terabytes per second (Tbps), 45% faster than the state-of-the-art interconnects in multichip packages.

The new building blocks are part of Marvell’s strategy to develop IP for chip designs that increase the bandwidth, performance and energy efficiency in data centers and upcoming autonomous vehicles. Marvell plans to use the technology to connect chiplets for its customers.

“Building things out into multiple chips doesn’t have to drive you to use a very expensive silicon interposer for interconnect,” Kuemerle said. “That capability to build with multiple chips in the automotive market is something I’m very interested in because we’re very quickly going to see the same trends we saw in the data center that are driving people to optimize power performance and cost. We’re on the cusp of automotive chips moving into multichip integration.”

The Marvell development is a vote of confidence in the chip industry’s latest 3-nm node that TSMC is starting to ramp up this year. Marvell is among TSMC’s top-ten customers, according to semiconductor industry analyst Arete Research.

The industry-first building blocks in the 3-nm node include 112G XSR SerDes, long-reach SerDes, PCIe Gen 6/ CXL 3.0 SerDes, and a 240 Tbps parallel die-to-die interconnect. Marvell was the first to offer 112G SerDes and data infrastructure products based on TSMC’s 5-nm process.

Marvell expects the new IP to initially benefit customers that are designing chips for data centers.

“Service providers are growing their network capacity by approximately 50% per year in the cloud and by over 100% for AI applications,” said Alan Weckel, an analyst with 650 Group. “Marvell’s successful production of 3-nm SerDes and interconnects marks the latest step in helping cloud service providers to stay ahead of the ever-escalating demand for higher speeds and more traffic.”

The technologies support semiconductor packaging options from standard and low-cost redistribution layers to silicon-based high-density interconnect. Marvell expects the interconnects to help cut overall power consumption in data centers by up to 20%.

Kuemerle said if Marvell were to find a way to take those components and bring them very close together on the same package, “we’re talking about an order of magnitude, a 10× improvement in power efficiency, just because we’ve got those devices close together and using optimized energy to communicate on the same package. Interconnect power oftentimes could be a third or maybe even a little bit more of the total power of that device. If you can cut a third of the power down by an order of magnitude, you go from 30 watts on a 100-watt chip to 3 watts with the same amount of interconnect.”

The carbon footprint of training an AI large language model is equal to around 300,000 kg of carbon dioxide emissions, according to an article in Nature. That’s comparable to 125 round-trip flights between New York and Beijing.

The new interconnects promise to reduce the carbon footprint in data centers.

Drivers and repeaters on a system can be eliminated by pulling components together, Kuemerle said. “You can get that 20-something percent benefit by eliminating the I/O to die-to-die. That involves a big rethink of how these systems are built. You solve some of the power consumption, but you’re creating a thermal challenge along with it. There’s a lot of activity within Marvell to find innovative thermal solutions.”

Automotive chips

Kuemerle said he sees potential for new technology in chips for the automotive industry.

“Automotive quality standards would tell you, ‘Stay the heck away from multichip.’ You can’t even stack vias on packets. What we’re seeing is more and more system-level safety that will actually enable these automotive applications with the right amount of security built into them to drive in a multichip environment.”

There are more opportunities for automotive ASICs and ADAS coupled with machine learning, he said. There are new activities going on around PCIe and using it for automotive support, he added.

Semiconductor companies are taking more interest in serving automotive customers that still face shortages of chips.

Marvell said that the 3-nm technology developed with TSMC may eventually be available in other foundries.

“Working across the industry, that standardization of this interconnect is really going to allow folks to have more and more choices for fabs, for premade components,” Kuemerle said. “That’s the vision that everybody has for this. You get to a point where you can pull a chip from fab A, a chip from fab B made by vendor C and integrate these all together and put it out.”

By: DocMemory
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