Fabless semiconductor company XMOS has designed the 4th generation of its Xcore architecture to be RISC-V compatible.

The company’s microarchitecture enables creation of a system-on-chip (SoC) using software programmability, allocating on-chip resources between DSP, AI acceleration and control functions, mixing and matching to meet the needs of the application, XMOS CEO Mark Lippett told EE Times.

“Our challenge is how do we deliver that through the most familiar design route to the largest community,” Lippett said.

XMOS’ architecture pre-dates RISC-V, but the company has been tracking RISC-V for a few years and saw the potential to create a RISC-V compatible Xcore—not a RISC-V Xcore, Lippett said, but one that’s compatible with the RISC-V ecosystem.

Mark Lippett XMOS

When XMOS was developing the previous (3rd) generation’s Xcore.ai, “it didn’t look like RISC-V was inevitable,” but when developing a 4th generation, “it became obvious RISC-V is here to stay and that our customers would value having a RISC-V instruction set and all the tools and facilities that came along with it,” he said.

The XMOS architecture has effectively been “skinned” with RISC-V. This means effectively including the RISC-V instruction set architecture (ISA) on top of the existing core design. Since RISC-V allows extensibility, that doesn’t mean XMOS can’t also add its secret sauce.

“From the hardware perspective, it was a relatively easy change, we didn’t give anything away in terms of the benefits of the Xcore,” he said. “There’s a register file change and instruction coding changes. The biggest challenge for us was moving an enormous amount of verification infrastructure onto a new ISA.”

The benefit to customers is software compatibility. Runtime code can easily be ported onto the XMOS platform, provided the customer wasn’t using any custom instructions on their previous hardware platform.

Will adding software compatibility encourage customers to port away from, as well as onto, the XMOS architecture?

“Our crown jewels are the ability to create the whole SoC using software,” Lippett said. “If a customer just dips in and uses the control piece, then they’re not really engaged on the platform as a whole and can move on. But our challenge is to always try to introduce customers to the special things we do and sell them on the benefits.”

XMOS can also benefit from the tools available in the RISC-V ecosystem, which Lippett said gives customers many more choices than what XMOS could achieve alone.

XMOS is building a RISC-V compatible chip on the new 4th-generation architecture, which it plans to sample around the end of this year. Historically, XMOS has only produced one tapeout per generation, since the design is flexible for different use cases. With different I/O and packaging options, this single tapeout becomes both the software programmable SoC version and also typically several ASSP versions, which are set up for specific use cases. While the ASSP version of the product doesn’t allow you to recompile the source code to change the configuration of the cores, there’s a level of configurability provided via an API.

The most recent ASSP on the current 3rd-generation XMOS platform is the XVF3800, which is set up for conferencing. Lippett said the XVF3800 is designed to meet “ambitious” voice quality standards from Zoom and Microsoft Teams. While the majority of compute on the chip is set up for DSP, some resources go to AI (for identifying speech, noise reduction, and optimizing DSP algorithms in real time).

XMOS XVF3800 dev kit

Smart farming

XMOS released its current 3rd-generation software programmable SoC, Xcore.ai, in 2020, targeting the AI-enabled IoT. One of the most surprising customer use cases Lippett has seen for this product so far has been a cough detector for industrial pig farming. The customer is working on a pilot run of small devices using AI to identify the sound of pigs coughing in their enclosures in order to better control any outbreak of illnesses in the livestock.

While other multi-chip solutions could do the job, there may not be an integrated SoC on the market that specifically matches the needs of a pig cough detector, Lippett said, adding that scalability and economics also play a big part.

“All these diverse applications in the IoT can be done by pulling together different technologies from different places. The question is, can they be done economically enough for the use case?” he said.

While it may sound like an obscure application, the pilot run was “hundreds of thousands of units” with potential to expand to the care of tens of millions of pigs with the same customer, Lippett said.

It’s not super-hard AI, it’s not ChatGPT, but it has genuine utility,” he added.

By: DocMemory
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