Over the last several years, we have seen the adoption of embedded FPGA (eFPGA) accelerating in production ASICs and SoCs. In fact, just last year we predicted that eFPGA LUTs would outship FPGA LUTs later this decade. This growth is being driven by several key factors:

*Customers are demanding performance and lower power.

*Chip development costs and design cycles continue to skyrocket.

*Designers want the ability to update SoCs over time to adapt to changing protocols, algorithms and customer needs.

*Application use cases are increasing as designers learn how to use eFPGA and see how others use it in innovative ways.

By integrating the FPGA into SoCs, ASICs and MCUs, designers now have the flexibility to make changes at any point in the chip’s life span, even in the customers’ systems.

This eliminates many expensive chip spins and enables chip designers to start addressing many customers and applications with the same chips. It also extends the life of chips and systems because designers are now able to update their chips as protocols and standards changed. In addition, while traditional FPGAs take seconds or longer to reconfigure, eFPGA allows customers to reconfigure in milliseconds or even microseconds.

We think 2023 will be another exciting year in eFPGA, and these are our top 5 predictions on what to expect:

*More companies will adopt eFPGA. The rate of adoption will continue to increase and more companies large and small will announce or ship products using eFPGA for a wide range of applications.

*Reconfigurable GPIO. An obvious and easy starting place for adoption is a small amount of eFPGA to enable support for any variation of UART, SPI or other GPIO interface. There are more variations that customers ask for than can be hardwired, and chips are becoming too expensive to do a mask version for even a major customer.

*Modular or Software-Controlled eFPGA. Some chip companies want to enable their own customers to program the eFPGA and are looking to make it easier to use. Rather than have the FPGA programmed as one large “blog” of Verilog, we can enable each ELFX 4K tile to run independently of the others with direct processor access so Verilog can be done as “subroutines” and run on any tile of the eFPGA. This increases the ease of use. Over time, an ecosystem of “subroutines” will become available from partners.

*AI and DSP will leverage eFPGA. By integrating eFPGA IP into an SoC, customers not only maintain the performance and programmability of an expensive and power-hungry FPGA or GPU but also benefit from much lower power consumption and cost. This is a significant advantage to systems customers that are designing their own ASICs, as well as chip companies that have traditionally had the DSP-FPGA or AI-GPU sitting next to their chip and can now integrate it to get more revenue and save their customer power and cost.

We expect a flurry of activity around this technology in the coming year. We’ve already seen many entities using eFPGA, such as the Air Force Research Laboratory, Boeing, DARPA, Datang Telecom/MorningCore Technology, Renesas/Dialog, Sandia National Labs, SiFive, Socionext and the U.S. Department of Defense. And customers have proven that designing with eFPGA is also fast. Some eFPGA vendors have even implemented eFPGA in six months.

In addition, because eFPGAs are scalable from 1K to 100Ks of LUTs, SoC designers can select exactly how much reconfigurability they need and, in many cases, can distribute multiple eFPGAs throughout the chip, locating them where needed rather than in a single large block.

The year of eFPGAs

This year might be one of the best years yet for eFPGAs, considering how mainstream they have become in chip design. This technology has evolved to the point that eFPGAs are now not only competitive in terms of density with traditional FPGAs but also offer lower cost and faster time to market. It also provides an extra level of security.

These benefits are game-changers for anyone designing complex chips.

By: DocMemory
Copyright © 2023 CST, Inc. All Rights Reserved