Samsung Electronics Co.'s memory chip head said on Tuesday the world’s top memory chipmaker will increase the memory density of its DRAM and NAND flash chips to “extreme levels” to improve their storage capacity and processing speed enough to be applied to hyperscale artificial intelligence.

“The 11-nanometer DRAM currently under development will achieve the industry’s highest level of memory density,” Lee Jung-bae, president and head of Samsung Electronics’ Device Solutions Division that oversees the memory chip business, said in an article posted on the company’s website.

His remarks came after Samsung recently unveiled the industry’s first and highest-capacity 32 gigabit DDR5 DRAM, using the industry’s leading 12-nanometer process technology.

“We are developing the highest layer of the 9th-generation V-NAND (vertical NAND) that can be implemented in a double-stack structure.”

The higher the energy density of memory chips, the fewer memory chips are needed to store the same amount of memory.

Alternatively, higher total memory capacity can be reached using the same number of higher-density DRAM chips.

Lee, holding a doctorate in electronics engineering from the country’s prestigious Seoul National University, said the rise of hyperscale AI in diverse sectors is creating demand for high-performance, high-capacity and low-power memory.

“In the coming era of below-10nm DRAM and 1,000-layer V-NAND, innovation in new structures and materials is crucial,” he noted.

For DRAM, Samsung is developing 3D stacked structures and new materials.

For V-NAND, it is working to stack up more cells on a printed circuit board with lower height, while minimizing interference between cells to achieve the smallest cell size in the industry.

“Going forward, we will continue to expand our high-capacity DRAM lineup and expand into solutions that can implement modules with a capacity of up to one terabyte,” Lee said.

One terabyte is 1,000 gigabytes.

Last month, Samsung released a 4-terabyte SSD in its high-performance V-NAND SSD 990 Pro series that improved data processing speed and capacity, primarily for gaming devices.

HBM

Lee expressed confidence in high-bandwidth memory (HBM), used to power AI devices like ChatGPT, data centers and machine learning platforms. Samsung is currently mass producing HBM3 and developing the next-generation HBM3E.

Moreover, it plans to develop the sixth-generation, top-performance HBM, or HBM4 DRAM, by 2025, alongside semiconductor chips tailored for customers, or changing storage capacity depending on customer demand.

LOW-POWER CHIPS

Lee said LPDDR DRAM, a low-power specialized chip, has achieved high enough performance to be applied to personal computers and data centers in the form of LPDDR package-based module products.

Samsung vows to up memory chip density to 'extreme levels'

Now as electronic gadgets such as smartphones process a greater amount of data, memory bottlenecks are emerging as a new challenge.

"To ease memory bottlenecks, we will apply PIM (processing in memory) and PNM (processing-near-memory) technologies, which implement data calculation functions inside memory chips or at the module level, to products such as HBM and CMM, thereby dramatically improving data calculation capabilities, while increasing power efficiency,” Lee added.

PB SSD

To further enhance the energy density of memory chips, Samsung will soon unveil a petabyte solid state drive (PB SSD), or hardware with a million gigabytes. It is a new memory type that allows for lower space and low energy consumption than traditional hard drivers.

It will showcase the latest memory semiconductor technology, products and future strategies at Samsung Memory Tech Day 2023 in Silicon Valley on Oct. 20.

By: DocMemory
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