Samsung, which last year claimed chip tech leadership by being the first to start production at the 3-nm node, is struggling to find customers, some of whom told EE Times the foundry’s leap ahead is too risky.

AI chipmakers Alphawave, Rebellions and Tenstorrent told EE Times they’ve chosen Samsung as their 4-nm foundry because the chipmaker is offering more attractive pricing and adding services to win customers from top rival Taiwan Semiconductor Manufacturing Co. (TSMC).

“At 4-nm FinFET, they [Samsung execs] have stabilized that process,” one of the Samsung customers told EE Times, speaking on condition of anonymity. “This isn’t 3-nm gate-all-around [nanosheet], where they still seem to be struggling a little bit to get yield and reliability.”

Samsung is wrestling with 3 nm because nanosheet 3D chip architecture was one of several steps too far, SemiAnalysis chief analyst Dylan Patel told EE Times. TSMC, which has been making 3-nm chips for Apple and MediaTek since early this year, won’t adopt nanosheet until 2025.

“If you look at Samsung, their 4 nm was less dense than TSMC’s 5 nm,” Patel said. “They’re jumping straight to something that is 3-nm density, also with the nanosheet structure. That’s one of the biggest hurdles.”

Samsung hasn’t worked out the “M0” contacts between metal interconnect and transistor layers at the 3-nm node, he said. “The metal-layer zero contacts have a lot of stochastics,” he said, noting a recent teardown of Samsung chips by research firm TechInsights.

TSMC and Intel have taken more cautious steps toward nanosheet, Patel said. TSMC will introduce nanosheet with its 2-nm node in 2025.

“If you look at what TSMC is indicating about 2 nm, it’s not a massive physical shrink versus 3 nm,” he said. “If you look at Intel’s [advanced-node] 18A and 20A, it’s not really a physical shrink versus TSMC’s 3 nm. It’s more a nanosheet change.”

Scaling stopped

The move from the current 3D architecture, FinFET, to nanosheet is a “big transition” where some CMOS components stop shrinking, according to Sri Samavedam, senior VP of CMOS technologies at R&D organization imec.

“SRAM is actually not scaling,” he told EE Times. “There’s going to be a period of two or three nodes of this gate-all-around/nanosheet architecture where SRAMs do not scale. You will see more disaggregation of the CMOS components like analog. I/Os are not scaling. Starting with gate-all-around … it’s not possible to build that.”

TSMC and Intel, taking “baby steps,” are probably better-positioned to deal with the nanosheet transition, according to Patel.

“SRAM shrinking is dead now, and that’s a big deal,” he said. “TSMC still has the densest SRAM.”

Even though Samsung moved to nanosheet first, TSMC’s been able to “stay ahead” with its FinFET node at 3 nm, he added.

Samsung declined to comment on its 3-nm production for foundry customers. In prepared remarks, the company did say, “We believe that Samsung gate-all-around (GAA) has the highest yield level among other comparable GAA technologies today. More importantly, we are the only foundry mass-producing chips using GAA process technology.”

Since Samsung started its 4-nm process in early 2021, a second generation has entered production with stable yield, Marco Chisari, head of Samsung’s U.S. foundry business, told EE Times. He expects third-generation, 4-nm products to enter production in the fourth quarter.

In October, AI chip designer Tenstorrent said it chose Samsung to make chiplets at the 4-nm node.

“We don’t want to be at the most advanced process node again for yield reasons, and we want to drive the benefits of a chiplet architecture because cost is a big issue for chiplets,” Tenstorrent COO Keith Witek told EE Times. “We think a sweet spot for us is Samsung. Their pricing is generally better than TSMC.”

Samsung will make 4-nm chiplets for Tenstorrent from its Taylor, Texas, fab by the end of next year, Chisari said.

Rebellions, a South Korean startup, used TSMC to produce its first 7-nm test chips but then switched to Samsung at 5 nm.

“We concluded at the time that if we collaborated with Samsung, especially in advanced nodes, we thought we could get a lot of support,” Rebellions CTO Jinwook Oh told EE Times. “They’ll pay more attention to your project.”

Rebellions said it is well-positioned for 5 nm and 4 nm.

“They [Samsung] haven’t found good customers yet and want to promote their technology,” Oh said. “We demonstrated that our 5-nm chip has very good performance. They want to pull more customers from outside of Korea with our showcase. That’s also true for 4 nm. That’s the reason I believe they have paid special attention to us.”

Advanced packaging

Demand for chiplets has spurred business for design startups while widening a shortage of advanced packaging capacity to stitch the silicon parts together.

“It’s new technology, and no one wants to build out the capital expenditure to build a very high-value line when you’re not even sure the equipment is going to work, the product is going to yield,” Witek said. “That’s a recipe for really crushing your margins. They’re bringing [advanced packaging capacity] online very slowly. Companies like Nvidia aren’t able to meet demand.”

To solve shortages, the packaging ecosystem must mature so that putting together pre-built chiplets into a new system can be done as quickly and easily as putting together a printed-circuit board with off-the-shelf chips, Alphawave CTO Tony Chan Carusone told EE Times.

“I think the foundries are going to ramp up their availability, ramp up their capacity to try to address the demand,” he added.

At 3 nm, there’s been an increase in activity from smaller players like Tenstorrent and Alphawave, Patel said.

“Companies that are not even $1 billion companies—profitable, but not even a billion dollars—are able to make small chiplets in 3 nm or test their IP in 3 nm before a license and proving the IP works,” he said. “Things like that are critical to proving whether your technology can be used at all. Companies like Alphawave, for example, are able to keep up despite the massive development cost because the demand is there for 3 nm.”

By: DocMemory
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