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Collaboration and Co-optimization Needed in Rapid AI and HPC

Monday, July 8, 2024

I recently attended the IEEE 74th Electronic Components and Technology Conference (ECTC) in Denver, Colorado. Held May 28-31, the event had an attendance of 2,000 registrants over four days. There were 379 technical papers presented, many with a focus on hybrid bonding, substrate scaling technologies for chiplets, and other key challenges related to the critical role that advanced packaging plays in enabling the fast-growing AI and high-performance computing (HPC) markets.

To say it bluntly, advanced packaging is sexy! From Taiwan Semiconductor Manufacturing Co. (TSMC) and Intel to Google and Meta, everyone was present because these are the technologies we need to power the next industrial revolution: AI.

In her keynote address, Keren Bergman of Columbia University discussed the unprecedented growth of AI applications in data centers—growing at a rate of six orders of magnitude in the last six years—and the need for optical interconnect technologies to increase energy efficiency and bandwidth density. Her presentation, “Petascale Photonic Chip Connectivity for Energy-Efficient AI Computing,” made a strong case for bringing photonics into compute sockets using heterogenous integration—a technology she expects to become commercially available no sooner than 2027.

Hybrid bonding was another hot topic covered widely at the conference; it is expected to be the successor to microbumps in devices requiring high-bandwidth data transmission. However, there are still a number of challenges that need to be addressed.

Designing next-generation, advanced high-density substrates was also a key topic at ECTC, with much talk about glass interposers—predicted to be the up-and-coming substrate once we hit the end of traditional approaches. This was the main focus of a very interesting panel session on substrate-scaling challenges that included Gang Duan from Intel, Kenneth Larsen from Synopsys, Kinya Ichikawa from TSMC, Harish Penmethsa from Applied Materials, Rozalia Beica from LQDX, Masahisa Ose from Resonac, and Yu-Po Wang from SPIL.

My takeaway was that while glass core substrates are an emerging technology, organic substrates still have a long life ahead. The focus right now should be on collaboration and co-optimization within the entire ecosystem. Design for manufacturing is critical—now more than ever—to achieve the highest possible performance of AI and HPC devices.

New to ECTC this year was a startup competition in the Plenary session on “The Future of the Semiconductor Industry: Emerging Startups and Material Innovations in Advanced Packaging,” chaired by Rozalia Beica of LQDX and Farhang Yazdani of Broadpack. I was honored to be invited to the jury panel lead by Yole Group’s Jeff Perkins. It was a “Shark Tank”-like session: several startup companies each gave a 10-minute pitch, followed by a three-minute Q&A from the jury panel. Participating startups included:

While choosing a winner was difficult, the panel ultimately selected Terecircuits. Silicon Valley-based Terecircuits is addressing the limitations of conventional pick-and-place assembly of ultra-small components for microLED panels and systems-in-packages (SiPs). Their laser-based technology can place multiple components on a surface simultaneously. Since thousands of components can be placed all at once, throughput actually increases as the geometry of the components shrinks in size.

I am looking forward to attending the 75th ECTC, which will be held May 27-30, 2025, at the Gaylord Texan Resort and Convention Center in Dallas. I hope to see you there!

By: DocMemory
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