Baya Systems is coming out of stealth mode to take the guess work out of chiplets.

In a briefing with EE Times, Nandan Nayampally, Baya’s chief commercial officer, said that with SoC and chiplet system design, as well as software development complexity exploding, there is also a growing need to accelerate analysis, design, and deployment of chiplets.

He said Baya’s broader agenda is to tackle the data movement bottleneck faced by AI workloads in heterogeneous computing environments, or what Baya said is now “intelligent compute.”

Nayampally said a more cohesive system is necessary to reduce data movement, even as more complex memory hierarchies and processing solutions are coupled together. Chiplets provide a solution but even with standardization, there is a need for tools to support an end-to-end workflow as software development for both them and SoCs gets more complex, he added.

Baya Systems sees a need for an end-to-end workflow to support chiplet architecture design from inception to implementation. (Source: Baya Systems)

Being able to fully exploit the benefits of chiplets comes with many challenges, Nayampally said, especially as systems get larger. “You need to be able to guarantee the performance. How do you do that across these different processing elements?”

Cost and power consumption are also considerations, he said, while time to market windows are shrinking. “Baya’s approach is to accelerate the analysis, design and development in deployment for multichip or multi cluster systems and more complex different processing elements together.”

Nayampally said the company’s algorithm-driven system architecture platform, WeaverPro, combined with its scalable IP and cache fabric, Weave IP, pulls together all the steps of building out chiplet architectures through data-driven design and optimization. “The fabric is designed in a multi-layered way where you can actually have the transport that is agnostic of protocol and the protocols are efficiently stacked on top of it,” he said.

Instead of parallelizing everything, common wires or specialized, dedicated wires can be used as needed, which addresses costs, logic and power, according to Nayampally.

Baya’s WeaverPro foundational software platforms include Cache Studio, which supports rapid design of efficient memory and cache architectures, freeform cache and memory hierarchy analysis, workload simulation and optimization of global system architectures, and chiplet partition.

Baya’s WeaverPro foundational software platforms include Cache Studio. (Source: Baya Systems)

Fabric Studio, meanwhile, can be used to design data-driven optimal on-die fabric microarchitectures, statically analyze and optimize design parameters and performance, and generate physically aware designs.

Although chiplets are ultimately highly customized depending on the needs of the system—especially in the era of AI—Nayampally said Baya’s goal is provide a modular tool set to support a chiplet workflow that starts from an architectural perspective all the way through to implementation. “EDA vendors do have some portions of it, but a lot of it is still missing,” he said.

The more a customer uses the Baya platform to build chiplet architectures, the more they can repurpose and reuse elements to speed up their design and deployment, Nayampally said, because it is modular.

The platform is also future proof and ready for multi-chiplets and packages, he added, even though most customers are not there yet.

Chiplets are not a new concept, but in the last few years they have been finding new problems to solve with semiconductor manufacturers turning to chiplets to counter the impact of the physical limitations of Moore’s Law.

The concept of chiplets goes back as far as the 1980s as multichip modules (MCMs) and even earlier in other configurations, noted Jim Handy, principal analyst with Objective Analysis, with Xilinx putting chiplets into a production environment about six years ago. “The idea has caught on in a big way, with the leading processor makers using the approach to expand the effective die size of server processors,” he told EE Times. “All this activity should help bring down costs by improving yields and manufacturability and to allow the approach to be used in an ever-broadening array of applications.”

Baya is not the only startup looking to ease chiplet deployment; Eliyan Corporation’s high-performance chiplet interconnect addresses what the company believes is a critical need for a cost-effective way of connecting homogeneous and heterogenous architectures on a standard organic substrate. Its “bunch of wires” (BoW) chiplet system can achieve similar bandwidth, power efficiency and latency as die-to-die implementations that use advanced packaging technologies.

Chiplet uptake in the last five years has spurred demand for best practices and led to the development of formal standards. The Universal Chiplet Interconnect Express (UCIe) 1.0 specification was released in the spring of 2022. It covers the die–to–die I/O physical layer, die–to–die protocols, and a software stack model leveraging PCI Express (PCIe) and Compute Express Link (CXL) industry standards.

Interest in chiplets has also spurred conferences that are focused on the technology, including EE Times’ Chiplets: Building the Future of SoCs, a virtual event running July 24-25.

By: DocMemory
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