NAND FLASH technology has been the primary solution for low-cost, high-density data storage for decades, revolutionizing markets from USB drives to servers. The non-volatile 2D or planar NAND FLASH memory has been the work horse of the solid-state storage industry for the first couple of decades. The transition from planar 2D to 3D NAND began at the start of the last decade with growth in cloud computing as well as smartphones.

3D NAND has become the most prominent non-volatile memory since the shipment of Samsung’s second-generation 32-word-line layer in 2014 and the introduction of the first commercial 24-word-line layer 128 Gbit chip in 2013. It took a few years to get those cost/capacity ratios right post which 3D NAND has become the defacto memory architecture across most of the computing applications.

The continued advancement in compute for training and inferencing generative AI models in the cloud and edge coupled with growing high-quality user-generated content via smartphone cameras will drive significant need for faster, higher capacity storage for at least the next two decades. AI smartphones, AI PCs, AI servers in enterprises, autonomous vehicles and robotics, will be key end-market drivers for 3D NAND growth. Consequently, the overall NAND FLASH memory market is expected to more than double to $93 billion by 2030, from $40 billion in 2023.

3D NAND has enabled higher bit growth rate but memory cost reduction per bit has been slowing due to the increased cost and complexities involved in scaling. For 3D NAND FLASH scaling in the future, word-line (WL) stacking will continue to be a key driver along with XYZ dimension shrink of the cell to alleviate the cost and device challenges introduced by the WL stacking.

However, 3D NAND flash vertical stack scaling poses challenges mostly on film deposition and etch, unlike devices scaling via feature size reduction. To pattern, isolate and connect vertically integrated 3D memory devices, difficult High Aspect Ratio (HAR) etches are required and the process gets complicated as we add more layers to the structure.

Reduced Etch Rate

The conventional HAR process slows down the etch rate with aspect ratio increase due to the attenuation of ion and neutral fluxes as a function of aspect ratio reducing the etching rate. This undesired effect is called aspect ratio-dependent etching (ARDE). This is one of the major inhibitors as chipmakers look to scale to higher layers of 3D NAND.

Variabilities in Profiles

The formation of cylindrical holes inside the films which house the storage devices, called high-aspect ratio (HAR) ONON (oxide and nitride) channel hole etch, is the most critical step in the etch process. Currently, the etch HAR is about 50:1, with diameter of approximately 100 nm and 5-6 µm deep and penetrates 128 layers. Further, as hundreds of layers of ONON films are being patterned to about 100 nm hole size, the etch aspect ratio (depth/width) will be pushed above 100:1 as we reach 1,000-layer 3D NAND by end of this decade.

This multiple tiering increases the difficulty to etch very deep and precise HAR cylindrical holes. Also, the formation of trillions of perfect channel holes from top to bottom at such a HAR with high uniformity and repeatability when employed in high volume production is a challenge. Understanding ion scattering and mask interactions through feature-scale modelling is another crucial area of focus to improve the channel hole profile which deteriorates due to profile bowing and tapering with increased aspect ratio.

Error-free Storage Requires Precise Cell Dimensions

Without major innovations in tools such as deposition and etch, the advanced layer 3D NAND evolution will struggle with cost efficiency, which could slow down the roadmap. Co-optimizing advanced deposition and etch technologies with the memory vendors is one of the ways to address the above challenges effectively. Innovative solutions like Cryogenic technology and advanced plasma chemistries can enhance high aspect ratio etching and minimize issues like twisting, roughness, and distortion, enabling more tiers for next-generation nodes.

Enhancing Etch Rate

The cryogenic etching process was initially developed in the 1980s and is re-emerging as a method of dry etching. The etch process is carried out at a low on-wafer temperature, typically below 0°C. Cryogenic etching helps increase adsorption of reactive species while limiting the lateral etch rate. Leveraging low-temperature benefits and different plasma chemistries to deliver increased high aspect ratio etch capability enhances the etching rate. Novel chemistries are used during the low temperature process to improve circularity and sidewall roughness of the etched holes. This technology also reduces the overall environmental impact of the etching process. The Cryogenic technology helps in addressing the above challenges stemming from the traditional HAR process.

Increasing the ion energy or adjusting the plasma chemistry to enhance the transport of neutrals and ions will be necessary to mitigate the ARDE effects. Innovation in plasma technology is crucial to drive ions much deeper with higher efficiency and will be necessary for enabling taller structures.

Perfectly Etched Channels Enable Vertical, Lateral, and Logical Scaling – Reducing Variabilities

Polymer deposition on the sidewalls of the mask is the main cause of sidewall roughness. Adopting leaner chemistry during low temperature etching improves mask morphology resulting in improved circularity and sidewall roughness of the etched holes. Further, capturing hole shape distortion and twisting through feature scale models is another powerful tool for understanding the etch profile and processes. Feature scale simulations coupled with reactor-scale modelling helps capture potential origins of feature hole distortions such as bowing, striation and twisting in addition to ARDE. This provides a recipe to manufacturers that controlling hole shape distortion early in the process can mitigate hole distortion transfer deeper in the etch.

Innovations in etch technology which utilizes the benefits of low temperature coupled with lean chemistry offers an additional window for improvement to NAND manufacturers unlike conventional etch processes. Leveraging such new technologies that result in highly precise and predictable etching process will enable the NAND vendors’ roadmap to scale to 1,000+ layers 3D NAND with consistent output, high volume and high-quality yields during production.

We are witnessing several innovations from equipment makers alongside chipmakers. One of the latest innovations that addresses most of the challenges from adopting the latest generation of cryogenic technology is “Lam Cryo 3.0” from Lam Research. It is fascinating to see how equipment makers such as Lam Research are leveraging the benefits of scalable high power and ion energy-confined plasma reactors, unique pulsed plasma technology and temperatures as low as -60oC to efficiently etch with tight profile control to enable deeper etching without compromising the feature shape.

Further, coupling the above techniques with AI to build advanced products for AI, Lam’s feature-scale models also capture the physics of the ion species, transport effect as well as the surface-level chemistry dependences in feature profile evolution and utilizes the vast amount of information in improving the solution every generation. Basically, these trained AI models are built on years of telemetry data, customer feedback and experience. They help simulate perfect recipes in different scenarios to optimize the etching performance within a pristine environment for achieving deeper etch performance.

Memory and storage are becoming critical to AI development and pose challenges in building the AI training hardware. The growth rate of future AI models is expected to exceed the capacity that current GPUs and DRAM can provide and as these models evolve and expand, the role of 3D NAND in large-capacity SSDs will become increasingly critical to maintain the exponential growth in performance from training to inferencing both in the cloud and with advanced NAND Flash at the edge for on-device inferencing.

Wrapping up

The demand for 3D NAND FLASH is expected to grow significantly over the next decade, with the potential for 1,000-word-line layer technology to enable die density to reach 100Gb/mm² by around 2030.

Scaling 3D NAND beyond 400 layers will introduce significant new challenges such as the need to etch higher aspect ratio features to enable more stacked wordlines and bits per cell, advancements in metallization, simplifying of integration and others.

This warrants consistent and accelerated innovation in etch and deposition technologies from the equipment vendors and meaningful investments from NAND chipmakers to adopt those advanced technologies and techniques to be successful in the AI era.

By: DocMemory
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