Intel’s 18A process is on schedule and developing as expected, Naga Chandrasekaran, Intel’s chief global operations officer and GM of the company’s foundry business, told yesterday’s UBS Global Technology and AI Conference.

“There’s nothing fundamentally challenging on this node now, it is about going through the remaining yield challenges, defect density challenges,” said Chandrasekaran, who joined Intel from Micron in July.

IMG_0566-150x150.jpegHe said that the plan is to sample 18A chips to customers in H1 2025 and start to ramp production at its Oregon fab in H2.

In September Intel said the defect density on 18A was 0.4 defects per cm^2 which compares with the 0.33 def/cm^2 defect density of TSMC’s N7 and N5 processes three quarters before mass production – which is about where 18A is now.

Intel had hoped to get ahead of TSMC at the 18A node. TSMC says it will be in production on its roughly equivalent N2 process in H2 2025.

Tom’s Hardware points out that TSMC’s N2 beats 18A for SRAM density – 31.8 Mb/mm^2 for Intel vs. 38 Mb/mm^2 for TSMC, but the comparative power metrics are not yet known.

18A has BSPD which N2 does not, and this may give Intel an advantage in logic density.

By: DocMemory
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