At its 2025 Europe Technology Symposium in Amsterdam, The Netherlands, TSMC announced that it is establishing a European design center in Munich, scheduled to open in Q3 2025 in order to support its European customers.

The company said that this will be its tenth design center, joining a network of design centers across Taiwan, the U.S., Canada, mainland China and Japan. TSMC said it chose Munich rather than Dresden—the latter is where it is building a fab for the N16 and N28 families—because Munich is close to its European customers.

According to the media briefing held today, the European Design Center will facilitate optimized chip designs for emerging applications in automotive, industrial applications, AI, telecommunications, IoT and beyond, as well as cultivate and expand expertise in automotive and non-volatile memory across the EU, focusing on advancing rapidly growing RRAM and MRAM innovations while supporting the industry to move beyond eFlash technology.

Technology roadmap plus N2/N3 tape-outs

From a technology roadmap viewpoint, the European event reiterated the developments in process technologies and packaging that it presented at the North American counterpart event in California last month (see TSMC Announces World-Leading A14 Node to Power AI), providing updates on A14, A16, N2, N3, as well as its 3D silicon stacking and advanced packaging. It also noted factors like integrated power delivery to improve power delivery density.

On N2, the company said that it is on track for production in the second half of 2025, with 256Mb SRAM average yield being over 90%. TSMC added that the number of N2 second-year new tape-outs has grown 4× versus N5 in the same period. Meanwhile N2P, with its 18% speed improvement (at the same power) and 36% power reduction (at the same speed), compared to N2, is on track for production in the second half of 2026.

Talking of tape-outs, the company said N3, its 3-nm process technology, is expected to be a high-volume and long-running node, with more than 70 new tape-outs as of April 2025. N3P entered nigh volume production in Q4 2024 as planned to succeed N3E (the Apple M4 SoC is built on TSMC’s N3E). Variants of N3 include N3X to push performance for client CPUs, N3C for enhancing cost-effectiveness of value-tier products and N3A for automotive applications like ADAS and self-driving technology. TSMC said N3A is currently undergoing final defect improvements and is on track for AEC-Q100 Grade 1 qualification, to make the process technology production ready later in 2025.

Interestingly, TSMC said that while the overall automotive market is soft, its growth is “fueling” accelerated adoption of advanced logic N4/N3 and N6RF for autonomous driving.

Robotics: the next frontier beyond AI

One of the themes that TSMC focused on was robotics, and how this will drive demand for more advanced silicon.

Beyond N2

To address these advanced applications, TSMC followed up on its presentation of its complementary field-effect transistor (CFET) design presented at the IEDM conference in San Francisco in December 2024. In today’s media briefing, TSMC said the CFET design is a promising scaling candidate, catering for the increasing demand for improved performance and reduced power consumption in a compact form factor.

The company added that by stacking the nFET and pFET vertically, CFET achieves nearly twice the density. At IEDM, TSMC presented an integrated nFET and pFET on the same wafer to enable the world’s smallest CFET inverter at 48-nm gate pitch.

By: DocMemory
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