The recent publication of JESD209-6, the latest Low Power Double Data Rate 6 (LPDDR6) standard released by the JEDEC Solid State Technology Association, aims to significantly boost memory speed and efficiency for various applications, including mobile devices and AI in the data center, while also addressing security concerns.

Key features and performance enhancements

Improvements on the performance front are designed to support AI applications and other high-performance workloads, including a dual sub-channel architecture that allows for flexible operation while maintaining a small access granularity of 32 bytes, Osamu Nagashima, chair of JEDEC’s LPDDR task group, told EE Times in a briefing.

LPDDR6 features also include two sub-channels per die, with 12 data signal lines (DQs) per sub-channel to optimize channel performance capabilities. Each sub-channel has four command/address (CA) signals that are optimized to reduce ball count and improve data access speed. “We are paying a lot of attention to the speed and total bandwidth that will help AI applications,” Nagashima said.

LPDDR6 also has a static efficiency mode designed to support high-capacity memory configurations and maximize bank resource utilization, as well as on-the-fly burst length control to support 32B & 64B flexible data access. Dynamic write non-target on-die termination (NT-ODT) enables the memory to adjust ODT based on workload demands, thereby improving signal integrity.

Power efficiency innovations

Balancing performance and power remains a key challenge for the industry, Nagashima said.

To improve power efficiency, LPDDR6 operates with a lower voltage and low power consumption capable VDD2 supply as compared to LPDDR5, and mandates two supplies for VDD2. Other power-saving features include alternating clock command inputs, which are used to enhance performance and efficiency, and Dynamic Voltage Frequency Scaling for Low Power (DVFS-LP), which lowers the VDD2 supply during low-frequency operation to reduce power consumption.

LPDDR6 also features a dynamic efficiency mode that utilizes a single sub-channel interface for low-power, low-bandwidth use cases, as well as support for both partial self and active refresh to reduce refresh power consumption.

Saving interface power has become increasingly important, Jeffrey Chung, co-vice chair of JEDEC’s JC-42.6 subcommittee for low power, said in the same briefing. The memory and the SoC talking to each other comprise the bulk of the power consumption. “Going wider but slower allows us to use less power-consuming transceivers and receivers.”

Nagashima said power consumption has always been a key industry demand, but it has become stronger in recent years, not just for mobile applications, but also for data center use cases.

Chung said that balancing power consumption and performance in data centers is being driven in part by cooling thresholds, particularly as systems approach the limits of air cooling and begin to require costlier liquid cooling methods.

Growing role in data centers

Data centers are following in the footsteps of mobile with a more rigorous focus on power savings. LPDDR’s lower average power at equivalent data rates now makes it increasingly attractive for data centers, especially in applications that don’t require the extensive capacity or features of DDR.

Chung said there’s a trend toward adopting LPDDR in low- and mid-end data centers and for AI accelerators that don’t require massive memory, while high-end systems may still rely on costly HBM.

Enhanced security and reliability

Just as power consumption is getting more attention in memory technologies, so is security.

LPDDR6 adds several security and reliability improvements over its previous iteration, including Per Row Activation Counting (PRAC) to support DRAM data integrity.

It also features a carve-out Meta mode, which is defined to enhance overall system reliability by allocating specific memory regions for critical tasks, as well as support for programmable link protection scheme and on-die error correction code (ECC).

Additionally, LPDDR6 is capable of supporting Command/Address (CA) parity, error scrubbing, and memory built-in self-test (MBIST) for enhanced error detection and system reliability.

Security is no longer considered an afterthought when designing a memory solution, Nagashima said, and the Row Hammer threat remains a primary driver for protecting DRAM.

He said that advanced features, such as per-row activation counting, command/address parity, and on-die ECC (Error Correction Code), together provide robust protection for data integrity and help counter threats like Row Hammer attacks.

LPDDR6 also supports enhanced metadata management, enabling the system to utilize additional data for error detection, correction, and recovery, thereby further bolstering system reliability.

Chung added that implementing features such as PRAC and expanded metadata support introduces some area and power overhead; however, this impact is minimal and does not impede standard system performance or bandwidth.

Furthermore, LPDDR6 supports robust encryption, preventing attackers from deciphering raw DRAM data, with encryption and decryption managed at the host side.

Despite the revolutionary demands AI is placing on memory, the latest updates to the LPDDR6 standard are evolutionary, Chung said, as revolutionary changes usually indicate a need to spin off a new standard, which was what led to the inception of LPDDR as well as other memories such as GDDR – dramatically updating a standard compromises backwards compatibility and demands a major retooling for the industry. “The concept of LPDD06 is to keep it as evolutionary as possible,” he said.

The LPDDR5 standard was updated by JEDEC in 2021, increasing speeds by 33% to 5833 Mbps as part of a focus on improving performance, power, and flexibility. The first iteration of LPDDR5 was released in the first half of 2019, operating at an input/output (I/O) rate of 6400 MT/s, 50% higher than the first version of LPDDR4, which came in at 3200 MT/s when it was published in 2014.

By: DocMemory
Copyright © 2023 CST, Inc. All Rights Reserved