Deca Technologies and Silicon Storage Technology (SST), a subsidiary of Microchip, have entered into a strategic agreement to develop comprehensive a non-volatile memory (NVM) chiplet package to help customers with the adoption of modular, multi-die systems.

The announcement comes as traditional monolithic chip designs are growing in complexity and cost, and this collaboration will look to combine Deca’s M-Series fan-out and Adaptive Patterning technologies with SST’s SuperFlash embedded flash technology.

Both companies are set to apply their system-level integration expertise to deliver a bundled offering that will help customers to design, verify and commercialise NVM chiplets – by providing greater architectural flexibility, they’re aiming to offer both technical and commercial advantages over traditional monolithic integration.

The collaborative solution will offer a modular, memory-centric foundation for advanced multi-die architectures.

The chiplet package leverages SST’s SuperFlash technology, along with the interface logic and physical design elements required to function as a self-contained chiplet. This is then paired with Adaptive Patterning-based redistribution layer (RDL) design rules, simulation flows, test strategies and manufacturing paths provided by Deca’s ecosystem of qualified partners.

Building on this foundation, Deca and SST will jointly support customers from early design through qualification and prototype manufacturing.

The companies said that by streamlining integration and accelerating design cycles, they aim to enable broader adoption of heterogeneous integration, engaging with customers globally to bring chiplet solutions to market.

“Chiplet integration is reshaping how the industry thinks about performance, scalability and time to market,” said Robin Davis, VP of Strategic Engagements & Applications at Deca. “Our partnership with SST empowers customers to develop a chiplet solution that combines different chips, process nodes, sizes and even die from multiple foundries delivering more efficient and cost-effective products.”

Chiplet technology has significant advantages and is a way for designers to go beyond traditional scaling to deliver enhanced functionality and performance.

Chiplets allow the reuse of existing IP and can facilitate the mixing of advanced process nodes with less expensive legacy geometries and by utilising the most appropriate die technology for a particular function, chiplets can offer a more versatile, efficient and economical pathway in terms of advanced semiconductor innovation.

“As our customers push the boundaries of Moore’s Law, they are expressing greater interest in chiplet- based solutions,” said Mark Reiten, Vice President of Microchip’s licensing business unit. “This partnership aims to deliver a comprehensive package of IP, simulation tools and advanced assembly and engineering services necessary for successful chiplet development and productisation.”

By: DocMemory
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